X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Fcpu_init.c;h=5bfab70b7edbac0d9ca15d124fab619db91c0192;hb=5a1095a830299aef8dd32495e505e92ab1749e89;hp=36ef23232ed044db5cf3316067b445d213c0f87a;hpb=080d897585428d0fd42c237abfb6746908f4effc;p=u-boot diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 36ef23232e..5bfab70b7e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -200,7 +200,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) #ifdef CONFIG_SYS_FSL_CPC #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) -static void disable_cpc_sram(void) +void disable_cpc_sram(void) { int i; @@ -225,15 +225,65 @@ static void disable_cpc_sram(void) } #endif -static void enable_cpc(void) +#if defined(T1040_TDM_QUIRK_CCSR_BASE) +#ifdef CONFIG_POST +#error POST memory test cannot be enabled with TDM +#endif +static void enable_tdm_law(void) +{ + int ret; + char buffer[HWCONFIG_BUFFER_SIZE] = {0}; + int tdm_hwconfig_enabled = 0; + + /* + * Extract hwconfig from environment since environment + * is not setup properly yet. Search for tdm entry in + * hwconfig. + */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret > 0) { + tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); + /* If tdm is defined in hwconfig, set law for tdm workaround */ + if (tdm_hwconfig_enabled) + set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, + LAW_TRGT_IF_CCSR); + } +} +#endif + +void enable_cpc(void) { int i; + int ret; u32 size = 0; - + u32 cpccfg0; + char buffer[HWCONFIG_BUFFER_SIZE]; + char cpc_subarg[16]; + bool have_hwconfig = false; + int cpc_args = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + /* Extract hwconfig from environment */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret > 0) { + /* + * If "en_cpc" is not defined in hwconfig then by default all + * cpcs are enable. If this config is defined then individual + * cpcs which have to be enabled should also be defined. + * e.g en_cpc:cpc1,cpc2; + */ + if (hwconfig_f("en_cpc", buffer)) + have_hwconfig = true; + } + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); + if (have_hwconfig) { + sprintf(cpc_subarg, "cpc%u", i + 1); + cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); + if (cpc_args == 0) + continue; + } + cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 @@ -280,6 +330,7 @@ static void invalidate_cpc(void) #else #define enable_cpc() #define invalidate_cpc() +#define disable_cpc_sram() #endif /* CONFIG_SYS_FSL_CPC */ /* @@ -368,12 +419,12 @@ void fsl_erratum_a007212_workaround(void) } #endif -void cpu_init_f (void) +ulong cpu_init_f(void) { + ulong flag = 0; extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); #endif #if defined(CONFIG_SECURE_BOOT) struct law_entry law; @@ -442,13 +493,14 @@ void cpu_init_f (void) #ifdef CONFIG_DEEP_SLEEP /* disable the console if boot from deep sleep */ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; #endif #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif + return flag; } /* Implement a dummy function for those platforms w/o SERDES */ @@ -462,10 +514,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); int enable_cluster_l2(void) { int i = 0; - u32 cluster; + u32 cluster, svr = get_svr(); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; + /* only the L2 of first cluster should be enabled as expected on T4080, + * but there is no EOC in the first cluster as HW sake, so return here + * to skip enabling L2 cache of the 2nd cluster. + */ + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0; @@ -486,7 +545,8 @@ int enable_cluster_l2(void) u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; u32 type = in_be32(&gur->tp_ityp[idx]); - if (type & TP_ITYP_AV) + if ((type & TP_ITYP_AV) && + TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) cluster_valid = 1; } @@ -511,88 +571,15 @@ int enable_cluster_l2(void) /* * Initialize L2 as cache. - * - * The newer 8548, etc, parts have twice as much cache, but - * use the same bit-encoding as the older 8555, etc, parts. - * */ -int cpu_init_r(void) +int l2cache_init(void) { __maybe_unused u32 svr = get_svr(); -#ifdef CONFIG_SYS_LBC_LCRR - fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; -#endif #ifdef CONFIG_L2_CACHE ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - extern int spin_table_compat; - const char *spin; -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 - ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; -#endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ - defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) - /* - * CPU22 and NMG_CPU_A011 share the same workaround. - * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both - * fixed in 2.0. NMG_CPU_A011 is activated by default and can - * be disabled by hwconfig with syntax: - * - * fsl_cpu_a011:disable - */ - extern int enable_cpu_a011_workaround; -#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 - enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); -#else - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; - int n, res; - - n = getenv_f("hwconfig", buffer, sizeof(buffer)); - if (n > 0) - buf = buffer; - - res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); - if (res > 0) - enable_cpu_a011_workaround = 0; - else { - if (n >= HWCONFIG_BUFFER_SIZE) { - printf("fsl_cpu_a011 was not found. hwconfig variable " - "may be too long\n"); - } - enable_cpu_a011_workaround = - (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || - (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); - } -#endif - if (enable_cpu_a011_workaround) { - flush_dcache(); - mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); - sync(); - } -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 - /* - * A-005812 workaround sets bit 32 of SPR 976 for SoCs running - * in write shadow mode. Checking DCWS before setting SPR 976. - */ - if (mfspr(L1CSR2) & L1CSR2_DCWS) - mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); -#endif - -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - spin = getenv("spin_table_compat"); - if (spin && (*spin == 'n')) - spin_table_compat = 0; - else - spin_table_compat = 1; -#endif puts ("L2: "); @@ -717,10 +704,96 @@ skip_l2: puts("disabled\n"); #endif + return 0; +} + +/* + * + * The newer 8548, etc, parts have twice as much cache, but + * use the same bit-encoding as the older 8555, etc, parts. + * + */ +int cpu_init_r(void) +{ + __maybe_unused u32 svr = get_svr(); +#ifdef CONFIG_SYS_LBC_LCRR + fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; +#endif +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + extern int spin_table_compat; + const char *spin; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 and NMG_CPU_A011 share the same workaround. + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both + * fixed in 2.0. NMG_CPU_A011 is activated by default and can + * be disabled by hwconfig with syntax: + * + * fsl_cpu_a011:disable + */ + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + int n, res; + + n = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (n > 0) + buf = buffer; + + res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); + if (res > 0) { + enable_cpu_a011_workaround = 0; + } else { + if (n >= HWCONFIG_BUFFER_SIZE) { + printf("fsl_cpu_a011 was not found. hwconfig variable " + "may be too long\n"); + } + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || + (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); + } +#endif + if (enable_cpu_a011_workaround) { + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); + sync(); + } +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running + * in write shadow mode. Checking DCWS before setting SPR 976. + */ + if (mfspr(L1CSR2) & L1CSR2_DCWS) + mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); +#endif + +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + spin = getenv("spin_table_compat"); + if (spin && (*spin == 'n')) + spin_table_compat = 0; + else + spin_table_compat = 1; +#endif + + l2cache_init(); #if defined(CONFIG_RAMBOOT_PBL) disable_cpc_sram(); #endif enable_cpc(); +#if defined(T1040_TDM_QUIRK_CCSR_BASE) + enable_tdm_law(); +#endif #ifndef CONFIG_SYS_FSL_NO_SERDES /* needs to be in ram since code uses global static vars */ @@ -888,6 +961,7 @@ skip_l2: } #endif + init_used_tlb_cams(); return 0; }