X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Fp5020_ids.c;h=b5d787c8e705e271c4b788ddb1fc0a2a6e220268;hb=390619ddb390b08d77a23dd6531d2ec4866fb1bd;hp=1255898483b7c1a15253f92b77d28e18234a6f16;hpb=4db2fa7f9446d0f2fe8db3d62184b1212fe22707;p=u-boot diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 1255898483..b5d787c8e7 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -1,46 +1,40 @@ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO( 1, 2, 1, 0), - SET_QP_INFO( 3, 4, 2, 1), - SET_QP_INFO( 5, 6, 3, 2), - SET_QP_INFO( 7, 8, 4, 3), - SET_QP_INFO( 9, 10, 5, 4), - SET_QP_INFO( 0, 0, 0, 5), - SET_QP_INFO( 0, 0, 0, 6), - SET_QP_INFO( 0, 0, 0, 7), - SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ - SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 0), + SET_QP_INFO(7, 8, 4, 1), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(11, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 0), + SET_QP_INFO(15, 16, 8, 1), + SET_QP_INFO(17, 18, 9, 0), + SET_QP_INFO(19, 20, 10, 1), +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_2(1, 199, 200), + SET_SRIO_LIODN_2(2, 201, 202), }; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), SET_BMAN_LIODN(32), +#endif SET_SDHC_LIODN(1, 64), @@ -52,10 +46,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), @@ -65,6 +59,7 @@ struct liodn_id_table liodn_tbl[] = { SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), }; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { @@ -75,6 +70,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 4, 14), SET_FMAN_RX_10G_LIODN(1, 0, 15), }; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif struct liodn_id_table sec_liodn_tbl[] = { @@ -89,6 +85,28 @@ struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), }; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct liodn_id_table raide_liodn_tbl[] = { + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), +}; +int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); +#endif + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), @@ -98,8 +116,10 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_PME [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), +#endif }; - -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);