X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Fu-boot-spl.lds;h=5ae7b3eedbc989b9d5636b27b70360ada39a70c3;hb=0cf876154922118d8fb1b4c30f527c95a113bef3;hp=acaa0939ab4e6add174dadc11dbb8f2d8b66c4f2;hpb=0d74665059943dc207df995e21a4767ca3e51a05;p=u-boot

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index acaa0939ab..5ae7b3eedb 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "config.h"	/* CONFIG_BOARDDIR */
+#include "config.h"
 
 OUTPUT_ARCH(powerpc)
 #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
@@ -57,6 +57,16 @@ SECTIONS
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
+#ifdef CONFIG_SPL_SKIP_RELOCATE
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : {
+		*(.sbss*)
+		*(.bss*)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+#endif
 
 /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
 #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
@@ -66,11 +76,16 @@ SECTIONS
 	} :text = 0xffff
 #else
 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
-	.bootpg ADDR(.text) + 0x1000 :
+#ifndef BOOT_PAGE_OFFSET
+#define BOOT_PAGE_OFFSET 0x1000
+#endif
+	.bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
 	{
 		arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
 	}
+#ifndef RESET_VECTOR_OFFSET
 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#endif
 #elif defined(CONFIG_FSL_ELBC)
 #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
 #else
@@ -81,6 +96,7 @@ SECTIONS
 	} = 0xffff
 #endif
 
+#ifndef CONFIG_SPL_SKIP_RELOCATE
 	/*
 	 * Make sure that the bss segment isn't linked at 0x0, otherwise its
 	 * address won't be updated during relocation fixups.
@@ -95,4 +111,5 @@ SECTIONS
 	}
 	. = ALIGN(4);
 	__bss_end = .;
+#endif
 }