X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc86xx%2FKconfig;h=fcac6584e89b2995f8ee3bb1d4eb485941a3bba1;hb=f1cc97764be4383d2aeb56d5ba5415439a1d5c97;hp=fe1859d206bc99e5875b6eef841d4de8c44cef65;hpb=0e6b7a28243175ae0874d53b6e6e4eff8548d71f;p=u-boot

diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index fe1859d206..fcac6584e8 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -10,18 +10,56 @@ choice
 
 config TARGET_SBC8641D
 	bool "Support sbc8641d"
+	select ARCH_MPC8641
+	select BOARD_EARLY_INIT_F
 
 config TARGET_MPC8610HPCD
 	bool "Support MPC8610HPCD"
+	select ARCH_MPC8610
+	select BOARD_EARLY_INIT_F
 
 config TARGET_MPC8641HPCN
 	bool "Support MPC8641HPCN"
+	select ARCH_MPC8641
 
 config TARGET_XPEDITE517X
 	bool "Support xpedite517x"
+	select ARCH_MPC8641
 
 endchoice
 
+config ARCH_MPC8610
+	bool
+	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
+	select SYS_FSL_HAS_DDR2
+
+config ARCH_MPC8641
+	bool
+	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
+	select SYS_FSL_HAS_DDR2
+
+config FSL_LAW
+	bool
+	help
+		Use Freescale common code for Local Access Window
+
+config SYS_CCSRBAR_DEFAULT
+	hex "Default CCSRBAR address"
+	default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
+	help
+		Default value of CCSRBAR comes from power-on-reset. It
+		is fixed on each SoC. Some SoCs can have different value
+		if changed by pre-boot regime. The value here must match
+		the current value in SoC. If not sure, do not change.
+config SYS_FSL_NUM_LAWS
+	int "Number of local access windows"
+	default 10 if ARCH_MPC8610 || ARCH_MPC8641
+	help
+		Number of local access windows. This is fixed per SoC.
+		If not sure, do not change.
+
 source "board/freescale/mpc8610hpcd/Kconfig"
 source "board/freescale/mpc8641hpcn/Kconfig"
 source "board/sbc8641d/Kconfig"