X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc86xx%2Fstart.S;h=4c29de61a24198dcc64bc8332fdfede210025e00;hb=d7b1970015e62d37b26bb6b94b64ae36728c63cc;hp=596053f8857e5bf6a306cdf11b0c86685bc2a200;hpb=6ca803750e1e08fce26e508f1c35170bf9259bb4;p=u-boot

diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S
index 596053f885..4c29de61a2 100644
--- a/arch/powerpc/cpu/mpc86xx/start.S
+++ b/arch/powerpc/cpu/mpc86xx/start.S
@@ -30,6 +30,7 @@
  *  board_init lies at a quite high address and when the cpu has
  *  jumped there, everything is ok.
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc86xx.h>
 #include <timestamp.h>
@@ -40,6 +41,7 @@
 
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include <asm/u-boot.h>
 
 #ifndef	CONFIG_IDENT_STRING
 #define CONFIG_IDENT_STRING ""
@@ -726,10 +728,12 @@ in_ram:
 	beq	4f
 3:	lwzu	r4,4(r3)
 	lwzux	r0,r4,r11
+	cmpwi	r0,0
 	add	r0,r0,r11
-	stw	r10,0(r3)
+	stw	r4,0(r3)
+	beq-	5f
 	stw	r0,0(r4)
-	bdnz	3b
+5:	bdnz	3b
 4:
 /* clear_bss: */
 	/*
@@ -848,8 +852,8 @@ setup_ccsrbar:
 	stw	r5, 0(r4) /* Store physical value of CCSR */
 	isync
 
-	lis	r5, TEXT_BASE@h
-	ori	r5,r5,TEXT_BASE@l
+	lis	r5, CONFIG_SYS_TEXT_BASE@h
+	ori	r5,r5,CONFIG_SYS_TEXT_BASE@l
 	lwz	r5, 0(r5)
 	isync
 
@@ -867,7 +871,7 @@ lock_ram_in_cache:
 	 */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:
@@ -902,7 +906,7 @@ unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:	icbi	r0, r3