X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc8xxx%2Ffsl_lbc.c;h=c1fe5790a31bed26380bcccb8bf9d801510e68e7;hb=8b485ba12b0defa0c4ed3559789250238f8331a8;hp=10fcd243f71346c33744fcdba0f3962f648fa476;hpb=38dba0c2ff685e3f8276a236bd70eaa09c84ead5;p=u-boot

diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index 10fcd243f7..c1fe5790a3 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -11,11 +11,11 @@
 
 #ifdef CONFIG_MPC85xx
 /* Boards should provide their own version of this if they use lbc sdram */
-void __sdram_init(void)
+static void __lbc_sdram_init(void)
 {
 	/* Do nothing */
 }
-void sdram_init(void) __attribute__((weak, alias("__sdram_init")));
+void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init")));
 #endif
 
 
@@ -28,12 +28,19 @@ void print_lbc_regs(void)
 		printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
 		       i, get_lbc_br(i), i, get_lbc_or(i));
 	}
+	printf("LBCR\t0x%08X\tLCRR\t0x%08X\n",
+		       get_lbc_lbcr(), get_lbc_lcrr());
 }
 
 void init_early_memctl_regs(void)
 {
 	uint init_br1 = 1;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+	/* Set the local bus monitor timeout value to the maximum */
+	clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
+#endif
+
 #ifdef CONFIG_MPC85xx
 	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
 	if (get_lbc_br(1) & BR_V)
@@ -53,8 +60,10 @@ void init_early_memctl_regs(void)
 #endif
 	/* now restrict to preliminary range */
 	if (init_br1) {
+#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
 		set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
 		set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
+#endif
 
 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 		set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
@@ -100,7 +109,7 @@ void init_early_memctl_regs(void)
 void upmconfig(uint upm, uint *table, uint size)
 {
 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	int i, mdr, mad, old_mad = 0;
+	int i, mad, old_mad = 0;
 	u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
 	u32 msel = BR_UPMx_TO_MSEL(upm);
 	u32 *mxmr = &lbc->mamr + upm;
@@ -131,7 +140,7 @@ void upmconfig(uint upm, uint *table, uint size)
 	for (i = 0; i < size; i++) {
 		out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
 		out_be32(&lbc->mdr, table[i]);
-		mdr = in_be32(&lbc->mdr);
+		(void)in_be32(&lbc->mdr);
 		*dummy = 0;
 		do {
 			mad = in_be32(mxmr) & MxMR_MAD_MSK;