X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc8xxx%2Ffsl_lbc.c;h=c1fe5790a31bed26380bcccb8bf9d801510e68e7;hb=8b485ba12b0defa0c4ed3559789250238f8331a8;hp=7598ebf4574c9d2e943bb95ddbc975ab97c659b5;hpb=e1ccf97c5d7651664d37c0c5aa243874b8851b2d;p=u-boot

diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index 7598ebf457..c1fe5790a3 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -11,7 +11,7 @@
 
 #ifdef CONFIG_MPC85xx
 /* Boards should provide their own version of this if they use lbc sdram */
-void __lbc_sdram_init(void)
+static void __lbc_sdram_init(void)
 {
 	/* Do nothing */
 }
@@ -28,6 +28,8 @@ void print_lbc_regs(void)
 		printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
 		       i, get_lbc_br(i), i, get_lbc_or(i));
 	}
+	printf("LBCR\t0x%08X\tLCRR\t0x%08X\n",
+		       get_lbc_lbcr(), get_lbc_lcrr());
 }
 
 void init_early_memctl_regs(void)
@@ -58,8 +60,10 @@ void init_early_memctl_regs(void)
 #endif
 	/* now restrict to preliminary range */
 	if (init_br1) {
+#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
 		set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
 		set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
+#endif
 
 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 		set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
@@ -105,7 +109,7 @@ void init_early_memctl_regs(void)
 void upmconfig(uint upm, uint *table, uint size)
 {
 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	int i, mdr, mad, old_mad = 0;
+	int i, mad, old_mad = 0;
 	u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
 	u32 msel = BR_UPMx_TO_MSEL(upm);
 	u32 *mxmr = &lbc->mamr + upm;
@@ -136,7 +140,7 @@ void upmconfig(uint upm, uint *table, uint size)
 	for (i = 0; i < size; i++) {
 		out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
 		out_be32(&lbc->mdr, table[i]);
-		mdr = in_be32(&lbc->mdr);
+		(void)in_be32(&lbc->mdr);
 		*dummy = 0;
 		do {
 			mad = in_be32(mxmr) & MxMR_MAD_MSK;