X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Fcache.h;h=d3a83910b6fce2c6449d30fa040f4b7c596686b2;hb=b3f0f63223ce42592499d71dcbd4d9ac18fb3e10;hp=53e8d05f50b1a251484e8be719ab216350e1c6b5;hpb=9d62f20d0861ef87460d073dc189c851715b46ae;p=u-boot

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 53e8d05f50..d3a83910b6 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -4,11 +4,10 @@
 #ifndef __ARCH_PPC_CACHE_H
 #define __ARCH_PPC_CACHE_H
 
-#include <linux/config.h>
 #include <asm/processor.h>
 
 /* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_8xx)
 #define	L1_CACHE_SHIFT	4
 #elif defined(CONFIG_PPC64BRIDGE)
 #define L1_CACHE_SHIFT	7
@@ -20,6 +19,12 @@
 
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
 /*
  * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  */
@@ -52,6 +57,12 @@ extern void unlock_ram_in_cache(void);
 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
 #endif /* __ASSEMBLY__ */
 
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+int l2cache_init(void);
+void enable_cpc(void);
+void disable_cpc_sram(void);
+#endif
+
 /* prep registers for L2 */
 #define CACHECRBA       0x80000823      /* Cache configuration register address */
 #define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */