X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Fconfig_mpc85xx.h;h=7a5487be884006ae0a5508af4a3c64b1b2aa9536;hb=d4683776728b2442379b15b4d22318e223a5124e;hp=34fc8fb5347f3a47217f414b50dbbb6b49710f0a;hpb=c534d2fdcf7aa80230a0f1ed54d5e3164ba595eb;p=u-boot diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 34fc8fb534..7a5487be88 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -24,6 +24,9 @@ /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_SEC_BE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SEC_MON_BE /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) @@ -38,6 +41,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8540) @@ -122,6 +126,7 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8572) @@ -132,6 +137,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1010) @@ -154,8 +160,10 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -171,6 +179,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1012 is single core version of P1021 */ @@ -188,13 +197,14 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -202,6 +212,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1014) @@ -219,6 +230,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_A004508 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -234,6 +246,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1020) @@ -246,6 +259,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -264,6 +278,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -273,12 +288,14 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #elif defined(CONFIG_P1023) #define CONFIG_MAX_CPUS 2 @@ -293,6 +310,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 @@ -309,13 +327,14 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -326,6 +345,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P2010 is single core version of P2020 */ @@ -338,6 +358,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P2020) @@ -353,8 +374,11 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -570,6 +594,7 @@ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_BSC9132) @@ -594,6 +619,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_A005434 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -657,8 +683,11 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007798 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) @@ -667,13 +696,22 @@ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ +#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ +#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_MAPLE +#define CONFIG_SYS_CPRI +#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_CPRI_CLK 3 +#define CONFIG_SYS_ULB_CLK 4 +#define CONFIG_SYS_ETVPE_CLK 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 @@ -684,18 +722,22 @@ #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_FSL_ERRATUM_A007212 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_MAX_CPUS 4 +#define CONFIG_MAX_DSP_CPUS 12 +#define CONFIG_NUM_DSP_CPUS 6 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 @@ -707,9 +749,9 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_CPUS 2 +#define CONFIG_MAX_DSP_CPUS 2 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 @@ -733,7 +775,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } -#define CONFIG_SYS_SDHC_CLOCK 0 #define CONFIG_SYS_FSL_NUM_LAWS 16 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 @@ -745,9 +786,13 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FSL_ERRATUM_A008044 #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 + per rcw field value */ +#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -761,6 +806,54 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_SFP_VER_3_0 + +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ +defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_E5500 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#endif +#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_MAX_CPUS 1 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLL 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CONFIG_SYS_FSL_NUM_LAWS 16 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 + per rcw field value */ +#define CONFIG_QBMAN_CLK_DIV 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 @@ -794,6 +887,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 + per rcw field value */ +#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 @@ -809,8 +905,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_PPC_C29X)