X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2FKconfig;h=6e29868f5f8f90fcb03e115e6375e02ab90a6997;hb=0c9075e9ad21caa43c524288d7def9e8b081fa11;hp=aa7cf779910edca925392e630622e4cde6cced95;hpb=fce7b2768364366bd4c4af9188186f6b3f9c2fe8;p=u-boot

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index aa7cf77991..6e29868f5f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -34,6 +34,33 @@ config TARGET_CHROMEBOOK_LINK
 
 endchoice
 
+config RAMBASE
+	hex
+	default 0x100000
+
+config RAMTOP
+	hex
+	default 0x200000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x10000
+
+config CPU_ADDR_BITS
+	int
+	default 36
+
+config HPET_ADDRESS
+	hex
+	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
+
+config SMM_TSEG
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+
 config ROM_SIZE
 	hex
 	default 0x800000
@@ -47,9 +74,18 @@ config HAVE_INTEL_ME
 	  SPI flash format. You will need to supply the me.bin file in
 	  your board directory.
 
+config X86_RAMTEST
+	bool "Perform a simple RAM test after SDRAM initialisation"
+	help
+	  If there is something wrong with SDRAM then the platform will
+	  often crash within U-Boot or the kernel. This option enables a
+	  very simple RAM test that quickly checks whether the SDRAM seems
+	  to work correctly. It is not exhaustive but can save time by
+	  detecting obvious failures.
+
 source "arch/x86/cpu/ivybridge/Kconfig"
 
-source "board/chromebook-x86/coreboot/Kconfig"
+source "board/coreboot/coreboot/Kconfig"
 
 source "board/google/chromebook_link/Kconfig"