X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2FKconfig;h=a995e32bb98cfc3dd1f5dc2a9efb4ed3b044516f;hb=4b5a4a0535e280279e8cab93ba6d4aad53896bda;hp=aaceaef8b5e9f438370d32718c8e22f982167e47;hpb=b5b6b0196017da0c2b4d483a2cd59be7810c1d7a;p=u-boot diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index aaceaef8b5..a995e32bb9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -4,91 +4,43 @@ menu "x86 architecture" config SYS_ARCH default "x86" -config USE_PRIVATE_LIBGCC - default y +choice + prompt "Mainboard vendor" + default VENDOR_EMULATION -config SYS_VSNPRINTF - default y +config VENDOR_COREBOOT + bool "coreboot" -choice - prompt "Target select" - -config TARGET_COREBOOT - bool "Support coreboot" - help - This target is used for running U-Boot on top of Coreboot. In - this case Coreboot does the early inititalisation, and U-Boot - takes over once the RAM, video and CPU are fully running. - U-Boot is loaded as a fallback payload from Coreboot, in - Coreboot terminology. This method was used for the Chromebook - Pixel when launched. - -config TARGET_CHROMEBOOK_LINK - bool "Support Chromebook link" - help - This is the Chromebook Pixel released in 2013. It uses an Intel - i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of - SDRAM. It has a Panther Point platform controller hub, PCIe - WiFi and Bluetooth. It also includes a 720p webcam, USB SD - reader, microphone and speakers, display port and 32GB SATA - solid state drive. There is a Chrome OS EC connected on LPC, - and it provides a 2560x1700 high resolution touch-enabled LCD - display. - -config TARGET_CHROMEBOX_PANTHER - bool "Support Chromebox panther (not available)" - select n - help - Note: At present this must be used with Coreboot. See README.x86 - for instructions. - - This is the Asus Chromebox CN60 released in 2014. It uses an Intel - Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a - Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also - includes a USB SD reader, four USB3 ports, display port and HDMI - video output and a 16GB SATA solid state drive. There is no Chrome - OS EC on this model. - -config TARGET_CROWNBAY - bool "Support Intel Crown Bay CRB" - help - This is the Intel Crown Bay Customer Reference Board. It contains - the Intel Atom Processor E6xx populated on the COM Express module - with 1GB DDR2 soldered down memory and a carrier board with the - Intel Platform Controller Hub EG20T, other system components and - peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. - -config TARGET_MINNOWMAX - bool "Support Intel Minnowboard MAX" - help - This is the Intel Minnowboard MAX. It contains an Atom E3800 - processor in a small form factor with Ethernet, micro-SD, USB 2, - USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. - It requires some binary blobs - see README.x86 for details. - - Note that PCIE_ECAM_BASE is set up by the FSP so the value used - by U-Boot matches that value. - -config TARGET_GALILEO - bool "Support Intel Galileo" - help - This is the Intel Galileo board, which is the first in a family of - Arduino-certified development and prototyping boards based on Intel - architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit - single-core, single-thread, Intel Pentium processor instrunction set - architecture (ISA) compatible, operating at speeds up to 400Mhz, - along with 256MB DDR3 memory. It supports a wide range of industry - standard I/O interfaces, including a full-sized mini-PCIe slot, - one 100Mb Ethernet port, a microSD card slot, a USB host port and - a USB client port. +config VENDOR_EFI + bool "efi" + +config VENDOR_EMULATION + bool "emulation" + +config VENDOR_GOOGLE + bool "Google" + +config VENDOR_INTEL + bool "Intel" endchoice -config DM_SPI - default y +# board-specific options below +source "board/coreboot/Kconfig" +source "board/efi/Kconfig" +source "board/emulation/Kconfig" +source "board/google/Kconfig" +source "board/intel/Kconfig" -config DM_SPI_FLASH - default y +# platform-specific options below +source "arch/x86/cpu/baytrail/Kconfig" +source "arch/x86/cpu/coreboot/Kconfig" +source "arch/x86/cpu/ivybridge/Kconfig" +source "arch/x86/cpu/qemu/Kconfig" +source "arch/x86/cpu/quark/Kconfig" +source "arch/x86/cpu/queensbay/Kconfig" + +# architecture-specific options below config SYS_MALLOC_F_LEN default 0x800 @@ -121,11 +73,29 @@ config X86_RESET_VECTOR bool default n +config RESET_SEG_START + hex + depends on X86_RESET_VECTOR + default 0xffff0000 + +config RESET_SEG_SIZE + hex + depends on X86_RESET_VECTOR + default 0x10000 + +config RESET_VEC_LOC + hex + depends on X86_RESET_VECTOR + default 0xfffffff0 + config SYS_X86_START16 hex depends on X86_RESET_VECTOR default 0xfffff800 +config DM_PCI_COMPAT + default y # Until we finish moving over to the new API + config BOARD_ROMSIZE_KB_512 bool config BOARD_ROMSIZE_KB_1024 @@ -225,157 +195,9 @@ config X86_RAMTEST to work correctly. It is not exhaustive but can save time by detecting obvious failures. -config MARK_GRAPHICS_MEM_WRCOMB - bool "Mark graphics memory as write-combining." - default n - help - The graphics performance may increase if the graphics - memory is set as write-combining cache type. This option - enables marking the graphics memory as write-combining. - -menu "Display" - -config FRAMEBUFFER_SET_VESA_MODE - prompt "Set framebuffer graphics resolution" - bool - help - Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) - -choice - prompt "framebuffer graphics resolution" - default FRAMEBUFFER_VESA_MODE_117 - depends on FRAMEBUFFER_SET_VESA_MODE - help - This option sets the resolution used for the coreboot framebuffer (and - bootsplash screen). - -config FRAMEBUFFER_VESA_MODE_100 - bool "640x400 256-color" - -config FRAMEBUFFER_VESA_MODE_101 - bool "640x480 256-color" - -config FRAMEBUFFER_VESA_MODE_102 - bool "800x600 16-color" - -config FRAMEBUFFER_VESA_MODE_103 - bool "800x600 256-color" - -config FRAMEBUFFER_VESA_MODE_104 - bool "1024x768 16-color" - -config FRAMEBUFFER_VESA_MODE_105 - bool "1024x7686 256-color" - -config FRAMEBUFFER_VESA_MODE_106 - bool "1280x1024 16-color" - -config FRAMEBUFFER_VESA_MODE_107 - bool "1280x1024 256-color" - -config FRAMEBUFFER_VESA_MODE_108 - bool "80x60 text" - -config FRAMEBUFFER_VESA_MODE_109 - bool "132x25 text" - -config FRAMEBUFFER_VESA_MODE_10A - bool "132x43 text" - -config FRAMEBUFFER_VESA_MODE_10B - bool "132x50 text" - -config FRAMEBUFFER_VESA_MODE_10C - bool "132x60 text" - -config FRAMEBUFFER_VESA_MODE_10D - bool "320x200 32k-color (1:5:5:5)" - -config FRAMEBUFFER_VESA_MODE_10E - bool "320x200 64k-color (5:6:5)" - -config FRAMEBUFFER_VESA_MODE_10F - bool "320x200 16.8M-color (8:8:8)" - -config FRAMEBUFFER_VESA_MODE_110 - bool "640x480 32k-color (1:5:5:5)" - -config FRAMEBUFFER_VESA_MODE_111 - bool "640x480 64k-color (5:6:5)" - -config FRAMEBUFFER_VESA_MODE_112 - bool "640x480 16.8M-color (8:8:8)" - -config FRAMEBUFFER_VESA_MODE_113 - bool "800x600 32k-color (1:5:5:5)" - -config FRAMEBUFFER_VESA_MODE_114 - bool "800x600 64k-color (5:6:5)" - -config FRAMEBUFFER_VESA_MODE_115 - bool "800x600 16.8M-color (8:8:8)" - -config FRAMEBUFFER_VESA_MODE_116 - bool "1024x768 32k-color (1:5:5:5)" - -config FRAMEBUFFER_VESA_MODE_117 - bool "1024x768 64k-color (5:6:5)" - -config FRAMEBUFFER_VESA_MODE_118 - bool "1024x768 16.8M-color (8:8:8)" - -config FRAMEBUFFER_VESA_MODE_119 - bool "1280x1024 32k-color (1:5:5:5)" - -config FRAMEBUFFER_VESA_MODE_11A - bool "1280x1024 64k-color (5:6:5)" - -config FRAMEBUFFER_VESA_MODE_11B - bool "1280x1024 16.8M-color (8:8:8)" - -config FRAMEBUFFER_VESA_MODE_USER - bool "Manually select VESA mode" - -endchoice - -# Map the config names to an integer (KB). -config FRAMEBUFFER_VESA_MODE - prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER - hex - default 0x100 if FRAMEBUFFER_VESA_MODE_100 - default 0x101 if FRAMEBUFFER_VESA_MODE_101 - default 0x102 if FRAMEBUFFER_VESA_MODE_102 - default 0x103 if FRAMEBUFFER_VESA_MODE_103 - default 0x104 if FRAMEBUFFER_VESA_MODE_104 - default 0x105 if FRAMEBUFFER_VESA_MODE_105 - default 0x106 if FRAMEBUFFER_VESA_MODE_106 - default 0x107 if FRAMEBUFFER_VESA_MODE_107 - default 0x108 if FRAMEBUFFER_VESA_MODE_108 - default 0x109 if FRAMEBUFFER_VESA_MODE_109 - default 0x10A if FRAMEBUFFER_VESA_MODE_10A - default 0x10B if FRAMEBUFFER_VESA_MODE_10B - default 0x10C if FRAMEBUFFER_VESA_MODE_10C - default 0x10D if FRAMEBUFFER_VESA_MODE_10D - default 0x10E if FRAMEBUFFER_VESA_MODE_10E - default 0x10F if FRAMEBUFFER_VESA_MODE_10F - default 0x110 if FRAMEBUFFER_VESA_MODE_110 - default 0x111 if FRAMEBUFFER_VESA_MODE_111 - default 0x112 if FRAMEBUFFER_VESA_MODE_112 - default 0x113 if FRAMEBUFFER_VESA_MODE_113 - default 0x114 if FRAMEBUFFER_VESA_MODE_114 - default 0x115 if FRAMEBUFFER_VESA_MODE_115 - default 0x116 if FRAMEBUFFER_VESA_MODE_116 - default 0x117 if FRAMEBUFFER_VESA_MODE_117 - default 0x118 if FRAMEBUFFER_VESA_MODE_118 - default 0x119 if FRAMEBUFFER_VESA_MODE_119 - default 0x11A if FRAMEBUFFER_VESA_MODE_11A - default 0x11B if FRAMEBUFFER_VESA_MODE_11B - default 0x117 if FRAMEBUFFER_VESA_MODE_USER - -endmenu - config HAVE_FSP bool "Add an Firmware Support Package binary" + depends on !EFI help Select this option to add an Firmware Support Package binary to the resulting U-Boot image. It is a binary blob which U-Boot uses @@ -407,42 +229,92 @@ config FSP_ADDR config FSP_TEMP_RAM_ADDR hex + depends on HAVE_FSP default 0x2000000 help - Stack top address which is used in FspInit after DRAM is ready and + Stack top address which is used in fsp_init() after DRAM is ready and CAR is disabled. -source "arch/x86/cpu/baytrail/Kconfig" - -source "arch/x86/cpu/coreboot/Kconfig" - -source "arch/x86/cpu/ivybridge/Kconfig" +config FSP_SYS_MALLOC_F_LEN + hex + depends on HAVE_FSP + default 0x100000 + help + Additional size of malloc() pool before relocation. -source "arch/x86/cpu/quark/Kconfig" +config FSP_USE_UPD + bool + depends on HAVE_FSP + default y + help + Most FSPs use UPD data region for some FSP customization. But there + are still some FSPs that might not even have UPD. For such FSPs, + override this to n in their platform Kconfig files. -source "arch/x86/cpu/queensbay/Kconfig" +config ENABLE_MRC_CACHE + bool "Enable MRC cache" + depends on !EFI && !SYS_COREBOOT + help + Enable this feature to cause MRC data to be cached in NV storage + to be used for speeding up boot time on future reboots and/or + power cycles. -config TSC_CALIBRATION_BYPASS - bool "Bypass Time-Stamp Counter (TSC) calibration" +config SMP + bool "Enable Symmetric Multiprocessing" default n help - By default U-Boot automatically calibrates Time-Stamp Counter (TSC) - running frequency via Model-Specific Register (MSR) and Programmable - Interval Timer (PIT). If the calibration does not work on your board, - select this option and provide a hardcoded TSC running frequency with - CONFIG_TSC_FREQ_IN_MHZ below. + Enable use of more than one CPU in U-Boot and the Operating System + when loaded. Each CPU will be started up and information can be + obtained using the 'cpu' command. If this option is disabled, then + only one CPU will be enabled regardless of the number of CPUs + available. + +config MAX_CPUS + int "Maximum number of CPUs permitted" + depends on SMP + default 4 + help + When using multi-CPU chips it is possible for U-Boot to start up + more than one CPU. The stack memory used by all of these CPUs is + pre-allocated so at present U-Boot wants to know the maximum + number of CPUs that may be present. Set this to at least as high + as the number of CPUs in your system (it uses about 4KB of RAM for + each CPU). + +config AP_STACK_SIZE + hex + depends on SMP + default 0x1000 + help + Each additional CPU started by U-Boot requires its own stack. This + option sets the stack size used by each CPU and directly affects + the memory used by this initialisation process. Typically 4KB is + enough space. - Normally this option should be turned on in a simulation environment - like qemu. +config HAVE_VGA_BIOS + bool "Add a VGA BIOS image" + help + Select this option if you have a VGA BIOS image that you would + like to add to your ROM. + +config VGA_BIOS_FILE + string "VGA BIOS image filename" + depends on HAVE_VGA_BIOS + default "vga.bin" + help + The filename of the VGA BIOS image in the board directory. -config TSC_FREQ_IN_MHZ - int "Time-Stamp Counter (TSC) running frequency in MHz" - depends on TSC_CALIBRATION_BYPASS - default 1000 +config VGA_BIOS_ADDR + hex "VGA BIOS image location" + depends on HAVE_VGA_BIOS + default 0xfff90000 help - The running frequency in MHz of Time-Stamp Counter (TSC). + The location of VGA BIOS image in the SPI flash. For example, base + address of 0xfff90000 indicates that the image will be put at offset + 0x90000 from the beginning of a 1MB flash device. menu "System tables" + depends on !EFI && !SYS_COREBOOT config GENERATE_PIRQ_TABLE bool "Generate a PIRQ table" @@ -454,6 +326,58 @@ config GENERATE_PIRQ_TABLE It specifies the interrupt router information as well how all the PCI devices' interrupt pins are wired to PIRQs. +config GENERATE_SFI_TABLE + bool "Generate a SFI (Simple Firmware Interface) table" + help + The Simple Firmware Interface (SFI) provides a lightweight method + for platform firmware to pass information to the operating system + via static tables in memory. Kernel SFI support is required to + boot on SFI-only platforms. If you have ACPI tables then these are + used instead. + + U-Boot writes this table in write_sfi_table() just before booting + the OS. + + For more information, see http://simplefirmware.org + +config GENERATE_MP_TABLE + bool "Generate an MP (Multi-Processor) table" + default n + help + Generate an MP (Multi-Processor) table for this board. The MP table + provides a way for the operating system to support for symmetric + multiprocessing as well as symmetric I/O interrupt handling with + the local APIC and I/O APIC. + +config GENERATE_ACPI_TABLE + bool "Generate an ACPI (Advanced Configuration and Power Interface) table" + default n + help + The Advanced Configuration and Power Interface (ACPI) specification + provides an open standard for device configuration and management + by the operating system. It defines platform-independent interfaces + for configuration and power management monitoring. + +config QEMU_ACPI_TABLE + bool "Load ACPI table from QEMU fw_cfg interface" + depends on GENERATE_ACPI_TABLE && QEMU + default y + help + By default, U-Boot generates its own ACPI tables. This option, if + enabled, disables U-Boot's version and loads ACPI tables generated + by QEMU. + +config GENERATE_SMBIOS_TABLE + bool "Generate an SMBIOS (System Management BIOS) table" + default y + help + The System Management BIOS (SMBIOS) specification addresses how + motherboard and system vendors present management information about + their products in a standard format by extending the BIOS interface + on Intel architecture systems. + + Check http://www.dmtf.org/standards/smbios for details. + endmenu config MAX_PIRQ_LINKS @@ -473,18 +397,6 @@ config IRQ_SLOT_COUNT should be enough for most boards. If this does not fit your board, change it according to your needs. -source "board/coreboot/coreboot/Kconfig" - -source "board/google/chromebook_link/Kconfig" - -source "board/google/chromebox_panther/Kconfig" - -source "board/intel/crownbay/Kconfig" - -source "board/intel/minnowmax/Kconfig" - -source "board/intel/galileo/Kconfig" - config PCIE_ECAM_BASE hex default 0xe0000000 @@ -499,13 +411,37 @@ config PCIE_ECAM_BASE assigned to PCI devices - i.e. the memory and prefetch regions, as passed to pci_set_region(). -config BOOTSTAGE +config PCIE_ECAM_SIZE + hex + default 0x10000000 + help + This is the size of memory-mapped address of PCI configuration space, + which is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, + so a default 0x10000000 size covers all of the 256 buses which is the + maximum number of PCI buses as defined by the PCI specification. + +config I8259_PIC + bool default y + help + Intel 8259 ISA compatible chipset incorporates two 8259 (master and + slave) interrupt controllers. Include this to have U-Boot set up + the interrupt correctly. -config BOOTSTAGE_REPORT +config I8254_TIMER + bool default y + help + Intel 8254 timer contains three counters which have fixed uses. + Include this to have U-Boot set up the timer correctly. -config CMD_BOOTSTAGE +config I8042_KEYB default y +config DM_KEYBOARD + default y + +source "arch/x86/lib/efi/Kconfig" + endmenu