X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fbaytrail%2Ffsp_configs.c;h=d49b8d27371b2afccc17713d957eddfd63a3c4ac;hb=ae1b939930b0fffc062bb99196ec22e19afcc7e8;hp=a72d615f21ff7f3bdad3673699b8bf0e96a0e733;hpb=f3b84a3032dd989a029320d9512846f48276db95;p=u-boot

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index a72d615f21..d49b8d2737 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -121,16 +121,23 @@ const struct pch_azalia_config azalia_config = {
 };
 
 /**
- * Override the FSP's UPD.
+ * Override the FSP's configuration data.
  * If the device tree does not specify an integer setting, use the default
  * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
  */
-void update_fsp_upd(struct upd_region *fsp_upd)
+void update_fsp_configs(struct fsp_config_data *config,
+			struct fspinit_rtbuf *rt_buf)
 {
+	struct upd_region *fsp_upd = &config->fsp_upd;
 	struct memory_down_data *mem;
 	const void *blob = gd->fdt_blob;
 	int node;
 
+	/* Initialize runtime buffer for fsp_init() */
+	rt_buf->common.stack_top = config->common.stack_top - 32;
+	rt_buf->common.boot_mode = config->common.boot_mode;
+	rt_buf->common.upd_data = &config->fsp_upd;
+
 	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
 
 	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);