X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fcoreboot%2Fpci.c;h=67eb14ce99406dd90c6bb819715a9d94f8f2d4c5;hb=622da1c36aee9c39075f2109848228a5737925c0;hp=6a3dd9391432017898e85c714100ee8e53232ce2;hpb=dee332ffb735f65ab922118791a583c17bb0b795;p=u-boot

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 6a3dd93914..67eb14ce99 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -10,32 +10,38 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
-			      struct pci_config_table *table)
-{
-	u8 secondary;
-	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-	hose->last_busno = max(hose->last_busno, (int)secondary);
-	pci_hose_scan_bus(hose, secondary);
-}
+DECLARE_GLOBAL_DATA_PTR;
 
-static struct pci_config_table pci_coreboot_config_table[] = {
-	/* vendor, device, class, bus, dev, func */
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
-		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
-	{}
+static const struct dm_pci_ops pci_x86_ops = {
+	.read_config	= pci_x86_read_config,
+	.write_config	= pci_x86_write_config,
 };
 
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-	hose->config_table = pci_coreboot_config_table;
-	hose->first_busno = 0;
-	hose->last_busno = 0;
+static const struct udevice_id pci_x86_ids[] = {
+	{ .compatible = "pci-x86" },
+	{ }
+};
+
+U_BOOT_DRIVER(pci_x86_drv) = {
+	.name		= "pci_x86",
+	.id		= UCLASS_PCI,
+	.of_match	= pci_x86_ids,
+	.ops		= &pci_x86_ops,
+};
 
-	pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
-		       PCI_REGION_MEM);
-	hose->region_count = 1;
-}
+static const struct udevice_id generic_pch_ids[] = {
+	{ .compatible = "intel,pch" },
+	{ }
+};
+
+U_BOOT_DRIVER(generic_pch_drv) = {
+	.name		= "pch",
+	.id		= UCLASS_PCH,
+	.of_match	= generic_pch_ids,
+};