X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fcoreboot%2Fpci.c;h=c9983f15889e4cdab4a55c41973c8aaba530a287;hb=892ff8e972efc7d4f42750e4fdbb2c2fefb78229;hp=0ddc97501b7807ef72c322d0e88ab5e2bf4b9846;hpb=452f50f7cff5d77db79ee3b11b4b3e19b166e6b0;p=u-boot

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 0ddc97501b..c9983f1588 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -6,40 +6,62 @@
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <pci.h>
 #include <asm/pci.h>
 
-static struct pci_controller coreboot_hose;
+DECLARE_GLOBAL_DATA_PTR;
 
-void pci_init_board(void)
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+			      struct pci_config_table *table)
 {
-	coreboot_hose.first_busno = 0;
-	coreboot_hose.last_busno = 0xff;
-	coreboot_hose.region_count = 0;
+	u8 secondary;
+	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+	hose->last_busno = max(hose->last_busno, (int)secondary);
+	pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_coreboot_config_table[] = {
+	/* vendor, device, class, bus, dev, func */
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
+	{}
+};
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+	hose->config_table = pci_coreboot_config_table;
+	hose->first_busno = 0;
+	hose->last_busno = 0;
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_PCI_MEM_BUS,
+		       CONFIG_PCI_MEM_PHYS,
+		       CONFIG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_PCI_IO_BUS,
+		       CONFIG_PCI_IO_PHYS,
+		       CONFIG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
 
-	pci_setup_type1(&coreboot_hose);
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_PREF_BUS,
+		       CONFIG_PCI_PREF_PHYS,
+		       CONFIG_PCI_PREF_SIZE,
+		       PCI_REGION_PREFETCH);
 
-	pci_register_hose(&coreboot_hose);
+	pci_set_region(hose->regions + 3,
+		       0,
+		       0,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
-	coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
+	hose->region_count = 4;
 }