X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Finterrupts.c;h=e733bcb30272fa0da847cac08ca318eac4ee61ee;hb=31bf0f57b2c322500ceccdc6a38b4a8edb7035f0;hp=e7887152f7b27f73559263092b5cc09b7fefbdf4;hpb=095593c0301399ae834050e2008862451a72b8b0;p=u-boot diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index e7887152f7..e733bcb302 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -34,6 +34,10 @@ #include #include #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; #define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -615,3 +619,31 @@ asm(".globl irq_common_entry\n" \ DECLARE_INTERRUPT(253) \ DECLARE_INTERRUPT(254) \ DECLARE_INTERRUPT(255)); + +#if defined(CONFIG_INTEL_CORE_ARCH) +/* + * Get the number of CPU time counter ticks since it was read first time after + * restart. This yields a free running counter guaranteed to take almost 6 + * years to wrap around even at 100GHz clock rate. + */ +u64 get_ticks(void) +{ + u64 now_tick = rdtsc(); + + if (!gd->arch.tsc_base) + gd->arch.tsc_base = now_tick; + + return now_tick - gd->arch.tsc_base; +} + +#define PLATFORM_INFO_MSR 0xce + +unsigned long get_tbclk(void) +{ + u32 ratio; + u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); + + ratio = (platform_info >> 8) & 0xff; + return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */ +} +#endif