X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fivybridge%2Fcpu.c;h=099cb94e5d280969afdbae977f1250724e81d6ce;hb=7e13f1d08fa85af97d11d9d13d506efdabd3db4d;hp=0f9390517ff92b0a6afb3983fffcaf54af52e60f;hpb=7e4a6ae62c7ee567ae43e94445e561b3ec8343b9;p=u-boot diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 0f9390517f..099cb94e5d 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -74,7 +74,7 @@ int arch_cpu_init_dm(void) /* * We should do as little as possible before the serial console is * up. Perhaps this should move to later. Our next lot of init - * happens in print_cpuinfo() when we have a console + * happens in checkcpu() when we have a console */ ret = set_flex_ratio_to_tdp_nominal(); if (ret) @@ -125,12 +125,10 @@ static void enable_usb_bar(struct udevice *bus) pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32); } -int print_cpuinfo(void) +int checkcpu(void) { enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; - char processor_name[CPU_MAX_NAME_LEN]; struct udevice *dev, *lpc; - const char *name; uint32_t pm1_cnt; uint16_t pm1_sts; int ret; @@ -146,8 +144,10 @@ int print_cpuinfo(void) } ret = cpu_common_init(); - if (ret) + if (ret) { + debug("%s: cpu_common_init() failed\n", __func__); return ret; + } /* Check PM1_STS[15] to see if we are waking from Sx */ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); @@ -167,8 +167,10 @@ int print_cpuinfo(void) /* Enable SPD ROMs and DDR-III DRAM */ ret = uclass_first_device_err(UCLASS_I2C, &dev); - if (ret) + if (ret) { + debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret); return ret; + } /* Prepare USB controller early in S3 resume */ if (boot_mode == PEI_BOOT_RESUME) { @@ -178,6 +180,14 @@ int print_cpuinfo(void) gd->arch.pei_boot_mode = boot_mode; + return 0; +} + +int print_cpuinfo(void) +{ + char processor_name[CPU_MAX_NAME_LEN]; + const char *name; + /* Print processor name */ name = cpu_get_name(processor_name); printf("CPU: %s\n", name);