X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fivybridge%2Fcpu.c;h=099cb94e5d280969afdbae977f1250724e81d6ce;hb=7e13f1d08fa85af97d11d9d13d506efdabd3db4d;hp=ab708dd776e80ef6eb0bb73a43381812a0537edc;hpb=f5fbbe95798dba8f1536892598afbf33b5c07b5f;p=u-boot diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index ab708dd776..099cb94e5d 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -4,6 +4,7 @@ * Graeme Russ, graeme.russ@gmail.com. * * Some portions from coreboot src/mainboard/google/link/romstage.c + * and src/cpu/intel/model_206ax/bootblock.c * Copyright (C) 2007-2010 coresystems GmbH * Copyright (C) 2011 Google Inc. * @@ -11,10 +12,17 @@ */ #include +#include #include #include +#include #include +#include +#include #include +#include +#include +#include #include #include #include @@ -22,155 +30,51 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) -{ - /* Enable port 80 POST on LPC */ - pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); - clrbits_le32(RCB_REG(GCS), 4); -} - -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) -{ - u8 reg8; - - pci_hose_read_config_byte(hose, dev, 0xdc, ®8); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_hose_write_config_byte(hose, dev, 0xdc, reg8); -} - -static void set_var_mtrr( - unsigned reg, unsigned base, unsigned size, unsigned type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - wrmsr(MTRRphysBase_MSR(reg), base | type, 0); - wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid, - (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1); -} - -static void enable_rom_caching(void) -{ - disable_caches(); - set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT); - enable_caches(); - - /* Enable Variable MTRRs */ - wrmsr(MTRRdefType_MSR, 0x800, 0); -} - static int set_flex_ratio_to_tdp_nominal(void) { - msr_t flex_ratio, msr; - u8 nominal_ratio; - /* Minimum CPU revision for configurable TDP support */ if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) return -EINVAL; - /* Check for Flex Ratio support */ - flex_ratio = msr_read(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return -EINVAL; - - /* Check for >0 configurable TDPs */ - msr = msr_read(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return -EINVAL; - - /* Use nominal TDP ratio for flex ratio */ - msr = msr_read(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return 0; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - msr_write(MSR_FLEX_RATIO, flex_ratio); - - /* Set flex ratio in soft reset data register bits 11:6 */ - clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, - (nominal_ratio & 0x3f) << 6); - - /* Set soft reset control to use register value */ - setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); - - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, PORT_RESET); - outb(0x6, PORT_RESET); - cpu_hlt(); - - /* Not reached */ - return -EINVAL; + return cpu_set_flex_ratio_to_tdp_nominal(); } -static void set_spi_speed(void) +int arch_cpu_init(void) { - u32 fdod; - - /* Observe SPI Descriptor Component Section 0 */ - writel(0x1000, RCB_REG(SPI_DESC_COMP0)); - - /* Extract the1 Write/Erase SPI Frequency from descriptor */ - fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); - fdod >>= 24; - fdod &= 7; + post_code(POST_CPU_INIT); - /* Set Software Sequence frequency to match */ - clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); + return x86_cpu_init_f(); } -int arch_cpu_init(void) +int arch_cpu_init_dm(void) { - const void *blob = gd->fdt_blob; struct pci_controller *hose; - int node; + struct udevice *bus, *dev; int ret; - post_code(POST_CPU_INIT); - timer_set_base(rdtsc()); - - ret = x86_cpu_init_f(); + post_code(0x70); + ret = uclass_get_device(UCLASS_PCI, 0, &bus); + post_code(0x71); if (ret) return ret; + post_code(0x72); + hose = dev_get_uclass_priv(bus); - ret = pci_early_init_hose(&hose); - if (ret) - return ret; + /* TODO(sjg@chromium.org): Get rid of gd->hose */ + gd->hose = hose; - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); - if (node < 0) - return -ENOENT; - ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); + ret = uclass_first_device_err(UCLASS_LPC, &dev); if (ret) return ret; - enable_spi_prefetch(hose, PCH_LPC_DEV); - - /* This is already done in start.S, but let's do it in C */ - enable_port80_on_lpc(hose, PCH_LPC_DEV); - - /* already done in car.S */ - if (false) - enable_rom_caching(); - - set_spi_speed(); - /* * We should do as little as possible before the serial console is * up. Perhaps this should move to later. Our next lot of init - * happens in print_cpuinfo() when we have a console + * happens in checkcpu() when we have a console */ ret = set_flex_ratio_to_tdp_nominal(); if (ret) @@ -179,6 +83,106 @@ int arch_cpu_init(void) return 0; } +#define PCH_EHCI0_TEMP_BAR0 0xe8000000 +#define PCH_EHCI1_TEMP_BAR0 0xe8000400 +#define PCH_XHCI_TEMP_BAR0 0xe8001000 + +/* + * Setup USB controller MMIO BAR to prevent the reference code from + * resetting the controller. + * + * The BAR will be re-assigned during device enumeration so these are only + * temporary. + * + * This is used to speed up the resume path. + */ +static void enable_usb_bar(struct udevice *bus) +{ + pci_dev_t usb0 = PCH_EHCI1_DEV; + pci_dev_t usb1 = PCH_EHCI2_DEV; + pci_dev_t usb3 = PCH_XHCI_DEV; + ulong cmd; + + /* USB Controller 1 */ + pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0, + PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32); + pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32); + + /* USB Controller 2 */ + pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0, + PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32); + pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32); + + /* USB3 Controller 1 */ + pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0, PCI_SIZE_32); + pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32); +} + +int checkcpu(void) +{ + enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; + struct udevice *dev, *lpc; + uint32_t pm1_cnt; + uint16_t pm1_sts; + int ret; + + /* TODO: cmos_post_init() */ + if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { + debug("soft reset detected\n"); + boot_mode = PEI_BOOT_SOFT_RESET; + + /* System is not happy after keyboard reset... */ + debug("Issuing CF9 warm reset\n"); + reset_cpu(0); + } + + ret = cpu_common_init(); + if (ret) { + debug("%s: cpu_common_init() failed\n", __func__); + return ret; + } + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { + debug("Resume from S3 detected, but disabled.\n"); + } else { + /* + * TODO: An indication of life might be possible here (e.g. + * keyboard light) + */ + } + post_code(POST_EARLY_INIT); + + /* Enable SPD ROMs and DDR-III DRAM */ + ret = uclass_first_device_err(UCLASS_I2C, &dev); + if (ret) { + debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret); + return ret; + } + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == PEI_BOOT_RESUME) { + uclass_first_device(UCLASS_LPC, &lpc); + enable_usb_bar(pci_get_controller(lpc->parent)); + } + + gd->arch.pei_boot_mode = boot_mode; + + return 0; +} + int print_cpuinfo(void) { char processor_name[CPU_MAX_NAME_LEN]; @@ -188,5 +192,14 @@ int print_cpuinfo(void) name = cpu_get_name(processor_name); printf("CPU: %s\n", name); + post_code(POST_CPU_INFO); + return 0; } + +void board_debug_uart_init(void) +{ + /* This enables the debug UART */ + pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, + PCI_SIZE_16); +}