X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fivybridge%2Fcpu.c;h=099cb94e5d280969afdbae977f1250724e81d6ce;hb=7e13f1d08fa85af97d11d9d13d506efdabd3db4d;hp=f0e733bc33101e1c798f5e258548f184b08ce8e9;hpb=9e66506d33eac67bfa814ccba1c9ccd06bb5b107;p=u-boot

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index f0e733bc33..099cb94e5d 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -17,8 +17,11 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <asm/cpu.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/lpc_common.h>
 #include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
@@ -33,51 +36,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int set_flex_ratio_to_tdp_nominal(void)
 {
-	msr_t flex_ratio, msr;
-	u8 nominal_ratio;
-
 	/* Minimum CPU revision for configurable TDP support */
 	if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
 		return -EINVAL;
 
-	/* Check for Flex Ratio support */
-	flex_ratio = msr_read(MSR_FLEX_RATIO);
-	if (!(flex_ratio.lo & FLEX_RATIO_EN))
-		return -EINVAL;
-
-	/* Check for >0 configurable TDPs */
-	msr = msr_read(MSR_PLATFORM_INFO);
-	if (((msr.hi >> 1) & 3) == 0)
-		return -EINVAL;
-
-	/* Use nominal TDP ratio for flex ratio */
-	msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
-	nominal_ratio = msr.lo & 0xff;
-
-	/* See if flex ratio is already set to nominal TDP ratio */
-	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
-		return 0;
-
-	/* Set flex ratio to nominal TDP ratio */
-	flex_ratio.lo &= ~0xff00;
-	flex_ratio.lo |= nominal_ratio << 8;
-	flex_ratio.lo |= FLEX_RATIO_LOCK;
-	msr_write(MSR_FLEX_RATIO, flex_ratio);
-
-	/* Set flex ratio in soft reset data register bits 11:6 */
-	clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
-			(nominal_ratio & 0x3f) << 6);
-
-	/* Set soft reset control to use register value */
-	setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
-
-	/* Issue warm reset, will be "CPU only" due to soft reset data */
-	outb(0x0, PORT_RESET);
-	outb(SYS_RST | RST_CPU, PORT_RESET);
-	cpu_hlt();
-
-	/* Not reached */
-	return -EINVAL;
+	return cpu_set_flex_ratio_to_tdp_nominal();
 }
 
 int arch_cpu_init(void)
@@ -111,7 +74,7 @@ int arch_cpu_init_dm(void)
 	/*
 	 * We should do as little as possible before the serial console is
 	 * up. Perhaps this should move to later. Our next lot of init
-	 * happens in print_cpuinfo() when we have a console
+	 * happens in checkcpu() when we have a console
 	 */
 	ret = set_flex_ratio_to_tdp_nominal();
 	if (ret)
@@ -162,41 +125,14 @@ static void enable_usb_bar(struct udevice *bus)
 	pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
 }
 
-static int report_bist_failure(void)
-{
-	if (gd->arch.bist != 0) {
-		post_code(POST_BIST_FAILURE);
-		printf("BIST failed: %08x\n", gd->arch.bist);
-		return -EFAULT;
-	}
-
-	return 0;
-}
-
-int print_cpuinfo(void)
+int checkcpu(void)
 {
 	enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
-	char processor_name[CPU_MAX_NAME_LEN];
 	struct udevice *dev, *lpc;
-	const char *name;
 	uint32_t pm1_cnt;
 	uint16_t pm1_sts;
 	int ret;
 
-	/* Halt if there was a built in self test failure */
-	ret = report_bist_failure();
-	if (ret)
-		return ret;
-
-	enable_lapic();
-
-	ret = microcode_update_intel();
-	if (ret)
-		return ret;
-
-	/* Enable upper 128bytes of CMOS */
-	writel(1 << 2, RCB_REG(RC));
-
 	/* TODO: cmos_post_init() */
 	if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
 		debug("soft reset detected\n");
@@ -207,15 +143,11 @@ int print_cpuinfo(void)
 		reset_cpu(0);
 	}
 
-	/* Early chipset init required before RAM init can work */
-	uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
-
-	ret = uclass_first_device_err(UCLASS_LPC, &lpc);
-	if (ret)
+	ret = cpu_common_init();
+	if (ret) {
+		debug("%s: cpu_common_init() failed\n", __func__);
 		return ret;
-
-	/* Cause the SATA device to do its early init */
-	uclass_first_device(UCLASS_DISK, &dev);
+	}
 
 	/* Check PM1_STS[15] to see if we are waking from Sx */
 	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
@@ -235,15 +167,27 @@ int print_cpuinfo(void)
 
 	/* Enable SPD ROMs and DDR-III DRAM */
 	ret = uclass_first_device_err(UCLASS_I2C, &dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	/* Prepare USB controller early in S3 resume */
-	if (boot_mode == PEI_BOOT_RESUME)
+	if (boot_mode == PEI_BOOT_RESUME) {
+		uclass_first_device(UCLASS_LPC, &lpc);
 		enable_usb_bar(pci_get_controller(lpc->parent));
+	}
 
 	gd->arch.pei_boot_mode = boot_mode;
 
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	char processor_name[CPU_MAX_NAME_LEN];
+	const char *name;
+
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
 	printf("CPU:   %s\n", name);