X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fivybridge%2Fmodel_206ax.c;h=81dedee2ec097125c86fdc85e0538cc7dbae45b8;hb=7e13f1d08fa85af97d11d9d13d506efdabd3db4d;hp=8b08c40bcb8943a6585f2422e7d2d044b9db414d;hpb=1131d4e22cf8f13d0dabaad7f1b84d9baffdfbd6;p=u-boot

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 8b08c40bcb..81dedee2ec 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -8,19 +8,22 @@
  */
 
 #include <common.h>
+#include <cpu.h>
+#include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
-#include <asm/lapic.h>
-#include <asm/lapic_def.h>
+#include <asm/cpu_x86.h>
 #include <asm/msr.h>
+#include <asm/msr-index.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/speedstep.h>
 #include <asm/turbo.h>
 #include <asm/arch/model_206ax.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void enable_vmx(void)
 {
 	struct cpuid_result regs;
@@ -280,18 +283,13 @@ static void configure_c_states(void)
 	msr_write(MSR_PP1_CURRENT_CONFIG, msr);
 }
 
-static int configure_thermal_target(void)
+static int configure_thermal_target(struct udevice *dev)
 {
 	int tcc_offset;
 	msr_t msr;
-	int node;
 
-	/* Find pointer to CPU configuration */
-	node = fdtdec_next_compatible(gd->fdt_blob, 0,
-				      COMPAT_INTEL_MODEL_206AX);
-	if (node < 0)
-		return -ENOENT;
-	tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
+	tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+				    "tcc-offset", 0);
 
 	/* Set TCC activaiton offset if supported */
 	msr = msr_read(MSR_PLATFORM_INFO);
@@ -365,7 +363,7 @@ static void set_max_ratio(void)
 		msr = msr_read(MSR_PLATFORM_INFO);
 		perf_ctl.lo = msr.lo & 0xff00;
 	}
-	msr_write(IA32_PERF_CTL, perf_ctl);
+	msr_write(MSR_IA32_PERF_CTL, perf_ctl);
 
 	debug("model_x06ax: frequency set to %d\n",
 	      ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
@@ -400,56 +398,7 @@ static void configure_mca(void)
 static unsigned ehci_debug_addr;
 #endif
 
-/*
- * Initialize any extra cores/threads in this package.
- */
-static int intel_cores_init(struct x86_cpu_priv *cpu)
-{
-	struct cpuid_result result;
-	unsigned threads_per_package, threads_per_core, i;
-
-	/* Logical processors (threads) per core */
-	result = cpuid_ext(0xb, 0);
-	threads_per_core = result.ebx & 0xffff;
-
-	/* Logical processors (threads) per package */
-	result = cpuid_ext(0xb, 1);
-	threads_per_package = result.ebx & 0xffff;
-
-	debug("CPU: %u has %u cores, %u threads per core\n",
-	      cpu->apic_id, threads_per_package / threads_per_core,
-	      threads_per_core);
-
-	for (i = 1; i < threads_per_package; ++i) {
-		struct x86_cpu_priv *new_cpu;
-
-		new_cpu = calloc(1, sizeof(*new_cpu));
-		if (!new_cpu)
-			return -ENOMEM;
-
-		new_cpu->apic_id = cpu->apic_id + i;
-
-		/* Update APIC ID if no hyperthreading */
-		if (threads_per_core == 1)
-			new_cpu->apic_id <<= 1;
-
-		debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);
-
-#if 0 && CONFIG_SMP && CONFIG_MAX_CPUS > 1
-		/* TODO(sjg@chromium.org): Start the new cpu */
-		if (!start_cpu(new_cpu)) {
-			/* Record the error in cpu? */
-			printk(BIOS_ERR, "CPU %u would not start!\n",
-			       new_cpu->apic_id);
-			new_cpu->start_err = 1;
-		}
-#endif
-	}
-
-	return 0;
-}
-
-int model_206ax_init(struct x86_cpu_priv *cpu)
+static int model_206ax_init(struct udevice *dev)
 {
 	int ret;
 
@@ -463,23 +412,12 @@ int model_206ax_init(struct x86_cpu_priv *cpu)
 	set_ehci_debug(0);
 #endif
 
-	/* Setup MTRRs based on physical address size */
-#if 0 /* TODO: Implement this */
-	struct cpuid_result cpuid_regs;
-
-	cpuid_regs = cpuid(0x80000008);
-	x86_setup_fixed_mtrrs();
-	x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
-	x86_mtrr_check();
-#endif
-
 #if CONFIG_USBDEBUG
 	set_ehci_debug(ehci_debug_addr);
 #endif
 
 	/* Enable the local cpu apics */
 	enable_lapic_tpr();
-	lapic_setup();
 
 	/* Enable virtualization if enabled in CMOS */
 	enable_vmx();
@@ -491,9 +429,11 @@ int model_206ax_init(struct x86_cpu_priv *cpu)
 	configure_misc();
 
 	/* Thermal throttle activation offset */
-	ret = configure_thermal_target();
-	if (ret)
+	ret = configure_thermal_target(dev);
+	if (ret) {
+		debug("Cannot set thermal target\n");
 		return ret;
+	}
 
 	/* Enable Direct Cache Access */
 	configure_dca_cap();
@@ -507,8 +447,51 @@ int model_206ax_init(struct x86_cpu_priv *cpu)
 	/* Enable Turbo */
 	turbo_enable();
 
-	/* Start up extra cores */
-	intel_cores_init(cpu);
+	return 0;
+}
+
+static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_IA32_PERF_CTL);
+	info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
+	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+		1 << CPU_FEAT_UCODE;
+
+	return 0;
+}
+
+static int model_206ax_get_count(struct udevice *dev)
+{
+	return 4;
+}
+
+static int cpu_x86_model_206ax_probe(struct udevice *dev)
+{
+	if (dev->seq == 0)
+		model_206ax_init(dev);
 
 	return 0;
 }
+
+static const struct cpu_ops cpu_x86_model_206ax_ops = {
+	.get_desc	= cpu_x86_get_desc,
+	.get_info	= model_206ax_get_info,
+	.get_count	= model_206ax_get_count,
+	.get_vendor	= cpu_x86_get_vendor,
+};
+
+static const struct udevice_id cpu_x86_model_206ax_ids[] = {
+	{ .compatible = "intel,core-gen3" },
+	{ }
+};
+
+U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
+	.name		= "cpu_x86_model_206ax",
+	.id		= UCLASS_CPU,
+	.of_match	= cpu_x86_model_206ax_ids,
+	.bind		= cpu_x86_bind,
+	.probe		= cpu_x86_model_206ax_probe,
+	.ops		= &cpu_x86_model_206ax_ops,
+};