X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fpci.c;h=c9c7637fa7d761f8a8e2da8d686510e9a8d81c6c;hb=d90384e834a551ef7b69b05f3be1bd103af87d38;hp=e23b233961cec277154b22941565990af7c87cab;hpb=a219daeafef4df1b219db68c80116d82113c82b2;p=u-boot

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index e23b233961..c9c7637fa7 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -19,101 +19,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pci_controller x86_hose;
-
-int pci_early_init_hose(struct pci_controller **hosep)
-{
-	struct pci_controller *hose;
-
-	hose = calloc(1, sizeof(struct pci_controller));
-	if (!hose)
-		return -ENOMEM;
-
-	board_pci_setup_hose(hose);
-	pci_setup_type1(hose);
-	hose->last_busno = pci_hose_scan(hose);
-	gd->hose = hose;
-	*hosep = hose;
-
-	return 0;
-}
-
-__weak int board_pci_pre_scan(struct pci_controller *hose)
-{
-	return 0;
-}
-
-__weak int board_pci_post_scan(struct pci_controller *hose)
-{
-	return 0;
-}
-
-void pci_init_board(void)
-{
-	struct pci_controller *hose = &x86_hose;
-
-	/* Stop using the early hose */
-	gd->hose = NULL;
-
-	board_pci_setup_hose(hose);
-	pci_setup_type1(hose);
-	pci_register_hose(hose);
-
-	board_pci_pre_scan(hose);
-	hose->last_busno = pci_hose_scan(hose);
-	board_pci_post_scan(hose);
-}
-
-static struct pci_controller *get_hose(void)
-{
-	if (gd->hose)
-		return gd->hose;
-
-	return pci_bus_to_hose(0);
-}
-
-unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
-{
-	uint8_t value;
-
-	pci_hose_read_config_byte(get_hose(), dev, where, &value);
-
-	return value;
-}
-
-unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
-{
-	uint16_t value;
-
-	pci_hose_read_config_word(get_hose(), dev, where, &value);
-
-	return value;
-}
-
-unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
-{
-	uint32_t value;
-
-	pci_hose_read_config_dword(get_hose(), dev, where, &value);
-
-	return value;
-}
-
-void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
-{
-	pci_hose_write_config_byte(get_hose(), dev, where, value);
-}
-
-void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
-{
-	pci_hose_write_config_word(get_hose(), dev, where, value);
-}
-
-void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
-{
-	pci_hose_write_config_dword(get_hose(), dev, where, value);
-}
-
 int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
 			ulong *valuep, enum pci_size_t size)
 {
@@ -151,3 +56,33 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
 
 	return 0;
 }
+
+void pci_assign_irqs(int bus, int device, u8 irq[4])
+{
+	pci_dev_t bdf;
+	int func;
+	u16 vendor;
+	u8 pin, line;
+
+	for (func = 0; func < 8; func++) {
+		bdf = PCI_BDF(bus, device, func);
+		pci_read_config16(bdf, PCI_VENDOR_ID, &vendor);
+		if (vendor == 0xffff || vendor == 0x0000)
+			continue;
+
+		pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin);
+
+		/* PCI spec says all values except 1..4 are reserved */
+		if ((pin < 1) || (pin > 4))
+			continue;
+
+		line = irq[pin - 1];
+		if (!line)
+			continue;
+
+		debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
+		      line, bus, device, func, 'A' + pin - 1);
+
+		pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+	}
+}