X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fpci.c;h=d2ec45a2403cba00839ed68378838407e153d303;hb=aa09505ba1677c25e83115375a6775a5eae444ef;hp=e23b233961cec277154b22941565990af7c87cab;hpb=1733259d25015c28c47990ec11af99b3f62f811c;p=u-boot

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index e23b233961..d2ec45a240 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -76,7 +76,8 @@ unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
 {
 	uint8_t value;
 
-	pci_hose_read_config_byte(get_hose(), dev, where, &value);
+	if (pci_hose_read_config_byte(get_hose(), dev, where, &value))
+		return -1U;
 
 	return value;
 }
@@ -85,7 +86,8 @@ unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
 {
 	uint16_t value;
 
-	pci_hose_read_config_word(get_hose(), dev, where, &value);
+	if (pci_hose_read_config_word(get_hose(), dev, where, &value))
+		return -1U;
 
 	return value;
 }
@@ -94,7 +96,8 @@ unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
 {
 	uint32_t value;
 
-	pci_hose_read_config_dword(get_hose(), dev, where, &value);
+	if (pci_hose_read_config_dword(get_hose(), dev, where, &value))
+		return -1U;
 
 	return value;
 }
@@ -151,3 +154,33 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
 
 	return 0;
 }
+
+void pci_assign_irqs(int bus, int device, u8 irq[4])
+{
+	pci_dev_t bdf;
+	int func;
+	u16 vendor;
+	u8 pin, line;
+
+	for (func = 0; func < 8; func++) {
+		bdf = PCI_BDF(bus, device, func);
+		vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
+		if (vendor == 0xffff || vendor == 0x0000)
+			continue;
+
+		pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
+
+		/* PCI spec says all values except 1..4 are reserved */
+		if ((pin < 1) || (pin > 4))
+			continue;
+
+		line = irq[pin - 1];
+		if (!line)
+			continue;
+
+		debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
+		      line, bus, device, func, 'A' + pin - 1);
+
+		x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+	}
+}