X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fquark%2Fdram.c;h=40c830af96b0f9e91d6aac25d0296c6d93bab48f;hb=6f192ddcbd8e13351a8f13365e7c714e7b61a79e;hp=9cac846c693114a9e303234b7979dd7ffe1c7223;hpb=e72d344386bf80738fab7a6bd37cb321f443093a;p=u-boot

diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
index 9cac846c69..40c830af96 100644
--- a/arch/x86/cpu/quark/dram.c
+++ b/arch/x86/cpu/quark/dram.c
@@ -7,12 +7,39 @@
 #include <common.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <malloc.h>
+#include <asm/mrccache.h>
+#include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/arch/mrc.h>
+#include <asm/arch/msg_port.h>
 #include <asm/arch/quark.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
+{
+	struct mrc_data_container *cache;
+	struct mrc_region entry;
+	int ret;
+
+	ret = mrccache_get_region(NULL, &entry);
+	if (ret)
+		return ret;
+
+	cache = mrccache_find_current(&entry);
+	if (!cache)
+		return -ENOENT;
+
+	debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
+	      cache->data, cache->data_size, cache->checksum);
+
+	/* copy mrc cache to the mrc_params */
+	memcpy(&mrc_params->timings, cache->data, cache->data_size);
+
+	return 0;
+}
+
 static int mrc_configure_params(struct mrc_params *mrc_params)
 {
 	const void *blob = gd->fdt_blob;
@@ -25,14 +52,15 @@ static int mrc_configure_params(struct mrc_params *mrc_params)
 		return -EINVAL;
 	}
 
-	/*
-	 * TODO:
-	 *
-	 * We need support fast boot (MRC cache) in the future.
-	 *
-	 * Set boot mode to cold boot for now
-	 */
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
+	if (mrc_params->boot_mode)
+		mrc_params->boot_mode = BM_COLD;
+	else
+		mrc_params->boot_mode = BM_FAST;
+#else
 	mrc_params->boot_mode = BM_COLD;
+#endif
 
 	/*
 	 * TODO:
@@ -96,6 +124,9 @@ static int mrc_configure_params(struct mrc_params *mrc_params)
 int dram_init(void)
 {
 	struct mrc_params mrc_params;
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	char *cache;
+#endif
 	int ret;
 
 	memset(&mrc_params, 0, sizeof(struct mrc_params));
@@ -111,6 +142,23 @@ int dram_init(void)
 	gd->ram_size = mrc_params.mem_size;
 	post_code(POST_DRAM);
 
+	/* variable range MTRR#2: RAM area */
+	disable_caches();
+	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
+		       0 | MTRR_TYPE_WRBACK);
+	msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
+		       (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
+	enable_caches();
+
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	cache = malloc(sizeof(struct mrc_timings));
+	if (cache) {
+		memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
+		gd->arch.mrc_output = cache;
+		gd->arch.mrc_output_len = sizeof(struct mrc_timings);
+	}
+#endif
+
 	return 0;
 }