X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Finclude%2Fasm%2Finterrupt.h;h=95a4de023efd639e78c8866e4c8921ad7b29b424;hb=2a605d4d8889ac5dd4c806b3a37ba75a80716e46;hp=3f46e0920a8646bea0b044ac2509a3b2346b3277;hpb=aaf5e825606a70ddc8fca8e366d8c16a6fd3cc7c;p=u-boot

diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
index 3f46e0920a..95a4de023e 100644
--- a/arch/x86/include/asm/interrupt.h
+++ b/arch/x86/include/asm/interrupt.h
@@ -13,13 +13,35 @@
 
 #include <asm/types.h>
 
+#define SYS_NUM_IRQS	16
+
+/* Architecture defined exceptions */
+enum x86_exception {
+	EXC_DE = 0,
+	EXC_DB,
+	EXC_NMI,
+	EXC_BP,
+	EXC_OF,
+	EXC_BR,
+	EXC_UD,
+	EXC_NM,
+	EXC_DF,
+	EXC_CSO,
+	EXC_TS,
+	EXC_NP,
+	EXC_SS,
+	EXC_GP,
+	EXC_PF,
+	EXC_MF = 16,
+	EXC_AC,
+	EXC_MC,
+	EXC_XM,
+	EXC_VE
+};
+
 /* arch/x86/cpu/interrupts.c */
 void set_vector(u8 intnum, void *routine);
 
-/* arch/x86/lib/interrupts.c */
-void disable_irq(int irq);
-void enable_irq(int irq);
-
 /* Architecture specific functions */
 void mask_irq(int irq);
 void unmask_irq(int irq);
@@ -27,4 +49,17 @@ void specific_eoi(int irq);
 
 extern char exception_stack[];
 
+/**
+ * configure_irq_trigger() - Configure IRQ triggering
+ *
+ * Switch the given interrupt to be level / edge triggered
+ *
+ * @param int_num legacy interrupt number (3-7, 9-15)
+ * @param is_level_triggered true for level triggered interrupt, false for
+ *	edge triggered interrupt
+ */
+void configure_irq_trigger(int int_num, bool is_level_triggered);
+
+void *x86_get_idt(void);
+
 #endif