X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Finclude%2Fasm%2Fmsr-index.h;h=b2a03f469a3804fe8a106c6c8f08429d8140c30b;hb=fc4f5cccd87abf4c72b13f64b49719fde9107cad;hp=38dbb3137aaf49fef5f93259372c539b35522f05;hpb=d81572c272d4b0980fb9b8a02e1357090b002398;p=u-boot

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 38dbb3137a..b2a03f469a 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -41,6 +41,9 @@
 #define EFER_FFXSR		(1<<_EFER_FFXSR)
 
 /* Intel MSRs. Some also available on other CPUs */
+#define MSR_PIC_MSG_CONTROL		0x2e
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+
 #define MSR_IA32_PERFCTR0		0x000000c1
 #define MSR_IA32_PERFCTR1		0x000000c2
 #define MSR_FSB_FREQ			0x000000cd
@@ -73,14 +76,27 @@
 #define MSR_IA32_MCG_STATUS		0x0000017a
 #define MSR_IA32_MCG_CTL		0x0000017b
 
+#define MSR_FLEX_RATIO			0x194
+#define  FLEX_RATIO_LOCK		(1 << 20)
+#define  FLEX_RATIO_EN			(1 << 16)
+
 #define MSR_IA32_MISC_ENABLES		0x000001a0
+#define MSR_TEMPERATURE_TARGET		0x1a2
 #define MSR_OFFCORE_RSP_0		0x000001a6
 #define MSR_OFFCORE_RSP_1		0x000001a7
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
 #define MSR_NHM_TURBO_RATIO_LIMIT	0x000001ad
 #define MSR_IVT_TURBO_RATIO_LIMIT	0x000001ae
 
+#define MSR_IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+
 #define MSR_LBR_SELECT			0x000001c8
 #define MSR_LBR_TOS			0x000001c9
+#define MSR_IA32_PLATFORM_DCA_CAP	0x1f8
 #define MSR_POWER_CTL			0x000001fc
 #define MSR_LBR_NHM_FROM		0x00000680
 #define MSR_LBR_NHM_TO			0x000006c0
@@ -147,7 +163,29 @@
 
 #define MSR_PKG_POWER_SKU_UNIT		0x00000606
 
+#define MSR_C_STATE_LATENCY_CONTROL_0	0x60a
+#define MSR_C_STATE_LATENCY_CONTROL_1	0x60b
+#define MSR_C_STATE_LATENCY_CONTROL_2	0x60c
+#define MSR_C_STATE_LATENCY_CONTROL_3	0x633
+#define MSR_C_STATE_LATENCY_CONTROL_4	0x634
+#define MSR_C_STATE_LATENCY_CONTROL_5	0x635
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
 #define MSR_PKG_POWER_LIMIT		0x00000610
+/* long duration in low dword, short duration in high dword */
+#define  PKG_POWER_LIMIT_MASK		0x7fff
+#define  PKG_POWER_LIMIT_EN		(1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT	17
+#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+
 #define MSR_PKG_ENERGY_STATUS		0x00000611
 #define MSR_PKG_PERF_STATUS		0x00000613
 #define MSR_PKG_POWER_INFO		0x00000614
@@ -165,7 +203,8 @@
 #define MSR_PP1_POWER_LIMIT		0x00000640
 #define MSR_PP1_ENERGY_STATUS		0x00000641
 #define MSR_PP1_POLICY			0x00000642
-
+#define MSR_CONFIG_TDP_NOMINAL		0x00000648
+#define MSR_TURBO_ACTIVATION_RATIO	0x0000064c
 #define MSR_CORE_C1_RES			0x00000660
 #define MSR_IACORE_RATIOS		0x0000066a
 #define MSR_IACORE_TURBO_RATIOS		0x0000066c