X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Finclude%2Fasm%2Fprocessor.h;h=cefc6339102e64ead58196812c85e161b0facc71;hb=7e4a6ae62c7ee567ae43e94445e561b3ec8343b9;hp=3e26202aa545504ac86f9c6278c66c9f8dd87482;hpb=88342103cccf73b39c764bfb1473e7bf29b52b88;p=u-boot

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 3e26202aa5..cefc633910 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -23,9 +23,31 @@
 
 #define X86_GDT_SIZE		(X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
 
+/* Length of the public header on Intel microcode blobs */
+#define UCODE_HEADER_LEN	0x30
+
 #ifndef __ASSEMBLY__
 
-#define PORT_RESET		0xcf9
+/*
+ * This register is documented in (for example) the Intel Atom Processor E3800
+ * Product Family Datasheet in "PCU - Power Management Controller (PMC)".
+ *
+ * RST_CNT: Reset Control Register (RST_CNT) Offset cf9.
+ *
+ * The naming follows Intel's naming.
+ */
+#define IO_PORT_RESET		0xcf9
+
+enum {
+	SYS_RST		= 1 << 1,	/* 0 for soft reset, 1 for hard reset */
+	RST_CPU		= 1 << 2,	/* initiate reset */
+	FULL_RST	= 1 << 3,	/* full power cycle */
+};
+
+/**
+ * x86_full_reset() - reset everything: perform a full power cycle
+ */
+void x86_full_reset(void);
 
 static inline __attribute__((always_inline)) void cpu_hlt(void)
 {