X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Finclude%2Fasm%2Fu-boot-x86.h;h=2340ef83323d11a8fd4f7b6dab159acb10078915;hb=329da4850c61994b83c025da68e1966a1259fd00;hp=9c143caf670b84653d14eda57bf70b936b965c35;hpb=d82477748d641e60ba3e1a0b55d98362aed70f80;p=u-boot diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 9c143caf67..2340ef8332 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -1,20 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _U_BOOT_I386_H_ #define _U_BOOT_I386_H_ 1 +struct global_data; + extern char gdt_rom[]; /* cpu/.../cpu.c */ int arch_cpu_init(void); int x86_cpu_init_f(void); int cpu_init_f(void); -void setup_gdt(gd_t *id, u64 *gdt_addr); +void setup_gdt(struct global_data *id, u64 *gdt_addr); /* * Setup FSP execution environment GDT to use the one we used in * arch/x86/cpu/start16.S and reload the segment registers. @@ -41,11 +42,10 @@ void x86_disable_caches(void); int x86_init_cache(void); void reset_cpu(ulong addr); ulong board_get_usable_ram_top(ulong total_size); -void dram_init_banksize(void); int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ -int setup_early_uart(void); +int setup_internal_uart(int enable); void setup_pcat_compatibility(void); @@ -56,7 +56,17 @@ u32 isa_map_rom(u32 bus_addr, int size); int video_bios_init(void); /* arch/x86/lib/fsp/... */ -int x86_fsp_init(void); + +/** + * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot + * + * At the end of pre-relocation phase, save the new stack address + * to CMOS and use it as the stack on next S3 boot for fsp_init() + * continuation function. + * + * @return: 0 if OK, -ve on error + */ +int fsp_save_s3_stack(void); void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); void board_init_f_r(void) __attribute__ ((noreturn));