X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fx86%2Flib%2Fpci_type1.c;h=13942a33f73b18088d3dc40dfb00865ca2dd3eff;hb=bceb9f0fc80c71b8b2a7371288199cdacca1bad9;hp=8ce5b33e3d235c115291634ea014a979445b8140;hpb=107b56bdd8e82b07458df11f8df4a01067512281;p=u-boot

diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c
index 8ce5b33e3d..13942a33f7 100644
--- a/arch/x86/lib/pci_type1.c
+++ b/arch/x86/lib/pci_type1.c
@@ -1,24 +1,8 @@
 /*
  * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
@@ -29,7 +13,7 @@
 #include <asm/io.h>
 #include <pci.h>
 
-#define cfg_read(val, addr, op)	*val = op((int)(addr))
+#define cfg_read(val, addr, op)		(*val = op((int)(addr)))
 #define cfg_write(val, addr, op)	op((val), (int)(addr))
 
 #define TYPE1_PCI_OP(rw, size, type, op, mask)				\
@@ -42,7 +26,6 @@ type1_##rw##_config_##size(struct pci_controller *hose,			\
 	return 0;							\
 }
 
-
 TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
 TYPE1_PCI_OP(read, word, u16 *, inw, 2)
 TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
@@ -51,7 +34,11 @@ TYPE1_PCI_OP(write, byte, u8, outb, 3)
 TYPE1_PCI_OP(write, word, u16, outw, 2)
 TYPE1_PCI_OP(write, dword, u32, outl, 0)
 
-void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+/* bus mapping constants (used for PCI core initialization) */
+#define PCI_REG_ADDR		0x00000cf8
+#define PCI_REG_DATA		0x00000cfc
+
+void pci_setup_type1(struct pci_controller *hose)
 {
 	pci_set_ops(hose,
 		    type1_read_config_byte,
@@ -61,6 +48,6 @@ void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
 		    type1_write_config_word,
 		    type1_write_config_dword);
 
-	hose->cfg_addr = (unsigned int *) cfg_addr;
-	hose->cfg_data = (unsigned char *) cfg_data;
+	hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
+	hose->cfg_data = (unsigned char *)PCI_REG_DATA;
 }