X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=asminc%2Fpet.inc;h=d165bb336cb74b603351d667df1db41e6a48f2e7;hb=HEAD;hp=43d52a5d5c406f26fcaa7c19741a12643d6e96bd;hpb=820b4dbc778ce26b51319c92cd79a1caeb3bb329;p=cc65

diff --git a/asminc/pet.inc b/asminc/pet.inc
index 43d52a5d5..d165bb336 100644
--- a/asminc/pet.inc
+++ b/asminc/pet.inc
@@ -61,8 +61,22 @@ NMIVec          := $0094
 ; ---------------------------------------------------------------------------
 ; I/O: 6522 VIA2
 
-VIA             := $E840
-VIA_PRB         := $E840
-VIA_PRA         := $E841
-VIA_DDRB        := $E842
-VIA_DDRA        := $E843
+VIA             := $E840        ; VIA base address
+VIA_PB          := VIA+$0       ; Port register B
+VIA_PA1         := VIA+$1       ; Port register A
+VIA_PRB         := VIA+$0       ; *** Deprecated ***
+VIA_PRA         := VIA+$1       ; *** Deprecated ***
+VIA_DDRB        := VIA+$2       ; Data direction register B
+VIA_DDRA        := VIA+$3       ; Data direction register A
+VIA_T1CL        := VIA+$4       ; Timer 1, low byte
+VIA_T1CH        := VIA+$5       ; Timer 1, high byte
+VIA_T1LL        := VIA+$6       ; Timer 1 latch, low byte
+VIA_T1LH        := VIA+$7       ; Timer 1 latch, high byte
+VIA_T2CL        := VIA+$8       ; Timer 2, low byte
+VIA_T2CH        := VIA+$9       ; Timer 2, high byte
+VIA_SR          := VIA+$A       ; Shift register
+VIA_CR          := VIA+$B       ; Auxiliary control register
+VIA_PCR         := VIA+$C       ; Peripheral control register
+VIA_IFR         := VIA+$D       ; Interrupt flag register
+VIA_IER         := VIA+$E       ; Interrupt enable register
+VIA_PA2         := VIA+$F       ; Port register A w/o handshake