X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2FRPXlite%2FRPXlite.c;h=dca53a46812b2a925aae58582a6da8397874c2cd;hb=67c3d9fb36bd0e66bd5cbf2719564e01f6459433;hp=f37e07b9234eff7e441c0d2956a97e7bcf019315;hpb=ea1fba136a4778b8f55e6b94a76a548cfad9f522;p=u-boot

diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c
index f37e07b923..dca53a4681 100644
--- a/board/RPXlite/RPXlite.c
+++ b/board/RPXlite/RPXlite.c
@@ -102,9 +102,9 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size10;
 
@@ -112,15 +112,15 @@ long int initdram (int board_type)
 		   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -137,7 +137,7 @@ long int initdram (int board_type)
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 			    SDRAM_MAX_SIZE);
 
 	return (size10);
@@ -156,7 +156,7 @@ long int initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;