X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2FRPXlite_dw%2FRPXlite_dw.c;h=d6fabf04eaca0585a20a7b8c4d84f0cee03eccb4;hb=68cf19aae48f2969ec70669604d0d776f02c8bc4;hp=86cf6c1d4d1e13a23bbddb62cffe0c49d683f194;hpb=e63c8ee3dcde0992377df434ab5af486dd866866;p=u-boot

diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c
index 86cf6c1d4d..d6fabf04ea 100644
--- a/board/RPXlite_dw/RPXlite_dw.c
+++ b/board/RPXlite_dw/RPXlite_dw.c
@@ -104,7 +104,7 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
 	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -124,7 +124,7 @@ long int initdram (int board_type)
 	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 	/*Disable Periodic timer A. */
 
- 	udelay(200);
+	udelay(200);
 
 	/* perform SDRAM initializsation sequence */
 
@@ -142,7 +142,7 @@ long int initdram (int board_type)
 	  * try 9 column mode
 	  */
 
-	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
 
 	/*
 	 * Final mapping: