X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fadder%2Fadder.c;h=87791deb5abcf2a5e0cbb64d3a642f883069b9e7;hb=5ba1ef507402bc5e344dc374203792a40f222e8a;hp=cab6e2f66aaf1f91adf0dff7702f725aa20587ef;hpb=2d24a3a787c2376c2c2c86a511eee78ef170923f;p=u-boot

diff --git a/board/adder/adder.c b/board/adder/adder.c
index cab6e2f66a..87791deb5a 100644
--- a/board/adder/adder.c
+++ b/board/adder/adder.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004 Arabella Software Ltd.
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * Support for Analogue&Micro Adder boards family.
@@ -26,9 +26,13 @@
 
 #include <common.h>
 #include <mpc8xx.h>
+#if defined(CONFIG_OF_LIBFDT)
+	#include <libfdt.h>
+#endif
 
 /*
- * SDRAM is single Samsung K4S643232F-T70 chip.
+ * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
+ *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
  * Minimal CPU frequency is 40MHz.
  */
 static uint sdram_table[] = {
@@ -53,7 +57,7 @@ static uint sdram_table[] = {
 	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
 	/* Refresh	(offset 0x30 in UPM RAM) */
-	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
 	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
@@ -61,10 +65,10 @@ static uint sdram_table[] = {
 	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
 };
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-	long int msize = CFG_SDRAM_SIZE;
-	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	long int msize;
+	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
@@ -72,11 +76,11 @@ long int initdram (int board_type)
 	/* Configure SDRAM refresh */
 	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
 
-	memctl->memc_mamr = (94 << 24) | CFG_MAMR;
-	memctl->memc_mar  = 0x0;
+	memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
 	udelay(200);
 
 	/* Run precharge from location 0x15 */
+	memctl->memc_mar = 0x0;
 	memctl->memc_mcr = 0x80002115;
 	udelay(200);
 
@@ -84,13 +88,18 @@ long int initdram (int board_type)
 	memctl->memc_mcr = 0x80002830;
 	udelay(200);
 
-	memctl->memc_mar = 0x88;
-	udelay(200);
-
 	/* Run MRS pattern from location 0x16 */
+	memctl->memc_mar = 0x88;
 	memctl->memc_mcr = 0x80002116;
 	udelay(200);
 
+	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
+	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
+	memctl->memc_or1  |= ~(msize - 1);
+
 	return msize;
 }
 
@@ -105,3 +114,11 @@ int checkboard( void )
 
 	return 0;
 }
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+}
+#endif