X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fads5121%2Fads5121.c;h=ba3d7d2a0d5547788c5bb4b6b44c9bceed12f77b;hb=dedec4cfc88eeadac616d558f6104cbe2e0d46aa;hp=289266529590812b6a52b04a068cdb02d10b21bd;hpb=10a3367955bc2033b288915f8f10d0e507fe2fa1;p=u-boot diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 2892665295..ba3d7d2a0d 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -26,6 +26,9 @@ #include #include #include +#ifdef CONFIG_MISC_INIT_R +#include +#endif /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ @@ -45,29 +48,12 @@ #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) -#define MPC5121_IOCTL_PSC6_0 (0x284/4) -#define MPC5121_IO_DIU_START (0x288/4) -#define MPC5121_IO_DIU_END (0x2fc/4) - -/* Functional pin muxing */ -#define MPC5121_IO_FUNC1 (0 << 7) -#define MPC5121_IO_FUNC2 (1 << 7) -#define MPC5121_IO_FUNC3 (2 << 7) -#define MPC5121_IO_FUNC4 (3 << 7) -#define MPC5121_IO_ST (1 << 2) -#define MPC5121_IO_DS_1 (0) -#define MPC5121_IO_DS_2 (1) -#define MPC5121_IO_DS_3 (2) -#define MPC5121_IO_DS_4 (3) - long int fixed_sdram(void); int board_early_init_f (void) { volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 lpcaw, tmp32; - volatile ioctrl512x_t *ioctl = &(im->io_ctrl); - int i; + u32 lpcaw; /* * Initialize Local Window for the CPLD registers access (CS2 selects @@ -91,28 +77,31 @@ int board_early_init_f (void) * Without this the flash identification routine fails, as it needs to issue * write commands in order to establish the device ID. */ - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; +#ifdef CONFIG_ADS5121_REV2 + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; +#else + if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) { + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + } else { + /* running from Backup flash */ + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32; + } +#endif + /* + * Configure Flash Speed + */ + *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG; /* * Enable clocks */ im->clk.sccr[0] = SCCR1_CLOCKS_EN; im->clk.sccr[1] = SCCR2_CLOCKS_EN; - /* Configure DIU clock pin */ - tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0]; - tmp32 &= ~0x1ff; - tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4; - ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32; - - /* Initialize IO pins (pin mux) for DIU function */ - for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++) - ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4); - return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { u32 msize = 0; @@ -133,7 +122,7 @@ long int fixed_sdram (void) u32 i; /* Initialize IO Control */ - im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR; + im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR; /* Initialize DDR Local Window */ im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; @@ -217,6 +206,7 @@ long int fixed_sdram (void) int misc_init_r(void) { u8 tmp_val; + extern int ads5121_diu_init(void); /* Using this for DIU init before the driver in linux takes over * Enable the TFP410 Encoder (I2C address 0x38) @@ -245,22 +235,69 @@ int misc_init_r(void) return 0; } +static iopin_t ioregs_init[] = { + /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ + { + IOCTL_SPDIF_TXCLK, 3, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* Set highest Slew on 9 PATA pins */ + { + IOCTL_PATA_CE1, 9, 1, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ + { + IOCTL_PSC0_0, 15, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=SPDIF_TXCLK */ + { + IOCTL_LPC_CS1, 1, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ + { + IOCTL_I2C1_SCL, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=DIU CLK */ + { + IOCTL_PSC6_0, 1, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=DIU_HSYNC */ + { + IOCTL_PSC6_1, 1, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ + { + IOCTL_PSC6_4, 26, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; int checkboard (void) { ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile unsigned long *reg; - int i; printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); + /* initialize function mux & slew rate IO inter alia on IO Pins */ + + + iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0])); - /* change the slew rate on all pata pins to max */ - reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]); - for (i = 0; i < 9; i++) - reg[i] |= 0x00000003; return 0; }