X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Famcc%2Fbamboo%2Fbamboo.c;h=6a50b393f462b56200fcf29a20ebeb9ae5fcde7e;hb=ad99abe8e721b948db3b6ab1c2cf10f3de5560e9;hp=84bbacf4c501f0e8f1a415f12934a5cab2e2ae12;hpb=c2120fbfbc4d1f6953228f86be8bdbf38bacfdab;p=u-boot

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 84bbacf4c5..6a50b393f4 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -12,11 +12,12 @@
 #include <asm/ppc440.h>
 #include "bamboo.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 int is_nand_selected(void);
 
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 /*************************************************************************
  *
  * Bamboo has one bank onboard sdram (plus DIMM)
@@ -178,7 +179,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
 	0,
 	0
 };
-#endif
 
 #if 0
 {	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
@@ -438,17 +438,11 @@ int checkboard(void)
 }
 
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
-	long dram_size;
+	gd->ram_size = spd_sdram();
 
-	dram_size = spd_sdram();
-
-	return dram_size;
-#else
-	return CONFIG_SYS_MBYTES_SDRAM << 20;
-#endif
+	return 0;
 }
 
 /*----------------------------------------------------------------------------+
@@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void)
 	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
 	{
 		update_ndfc_ios(gpio_tab);
-
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
 		      SDR0_CUST0_NDFC_ENABLE	|
 		      SDR0_CUST0_NDFC_BW_8_BIT	|
 		      SDR0_CUST0_NDFC_ARE_MASK	|
 		      SDR0_CUST0_CHIPSELGAT_EN1 |
 		      SDR0_CUST0_CHIPSELGAT_EN2);
-#else
-		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
-		      SDR0_CUST0_NDFC_ENABLE	|
-		      SDR0_CUST0_NDFC_BW_8_BIT	|
-		      SDR0_CUST0_NDFC_ARE_MASK	|
-		      SDR0_CUST0_CHIPSELGAT_EN0 |
-		      SDR0_CUST0_CHIPSELGAT_EN2);
-#endif
-
 		ndfc_selection_in_fpga();
 	}
 	else