X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Famcc%2Fkilauea%2Fkilauea.c;h=abfaa1eee098aeeabb9ec834674018f9075247dd;hb=d44a5f51288aec60c6bdb4ac939d75c24e5bf9c2;hp=2ee896abd9669c73fae73df27a6a6c18b71166ee;hpb=8d79953d03e6c5b24215609997dafe4daa623cd6;p=u-boot diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 2ee896abd9..abfaa1eee0 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -2,32 +2,17 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include -#include -#include +#include +#include #include #include #include #include +#include #if defined(CONFIG_PCI) #include @@ -36,7 +21,38 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static int board_cpld_version(void) +{ + u32 cpld; + + cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE); + if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) { + /* + * Magic not found -> "old" CPLD revision which needs + * the "old" EBC configuration + */ + mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) | + EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE | + EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) | + EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) | + EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED | + EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); + + /* + * Return 0 for "old" CPLD version + */ + return 0; + } + + /* + * Magic found -> "new" CPLD revision which needs no new + * EBC configuration + */ + return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8; +} /* * Board early initialization function @@ -158,33 +174,33 @@ int board_early_init_f (void) | interrupts again. +-------------------------------------------------------------------*/ - mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic2er, 0x00000000); /* disable all interrupts */ - mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ - - mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic1er, 0x00000000); /* disable all interrupts */ - mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ - - mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ - mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ + + mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ /* Except cascade UIC0 and UIC1 */ - mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ - mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ /* * Note: Some cores are still in reset when the chip starts, so @@ -192,19 +208,12 @@ int board_early_init_f (void) */ mtsdr(SDR0_SRST, 0); - /* - * Configure FPGA register with PCIe reset - */ - out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */ - mdelay(50); - out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */ - /* Configure 405EX for NAND usage */ val = SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NRB_BUSY | - (0x80000000 >> (28 + CFG_NAND_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); mtsdr(SDR0_CUST0, val); /* @@ -214,15 +223,29 @@ int board_early_init_f (void) val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; mtsdr(SDR0_PFC1, val); + /* + * The CPLD version detection has to be the first access to + * the CPLD, so we need to make this access this early and + * save the CPLD version for later. + */ + gd->board_type = board_cpld_version(); + + /* + * Configure FPGA register with PCIe reset + */ + out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ + mdelay(50); + out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ + return 0; } int misc_init_r(void) { -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); #endif @@ -230,163 +253,57 @@ int misc_init_r(void) return 0; } -int board_emac_count(void) +static int is_405exr(void) { u32 pvr = get_pvr(); + if (pvr & 0x00000004) + return 0; /* bit 2 set -> 405EX */ + + return 1; /* bit 2 cleared -> 405EXr */ +} + +int board_emac_count(void) +{ /* * 405EXr only has one EMAC interface, 405EX has two */ - if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + if (is_405exr()) return 1; else return 2; } -static int board_pcie_count(void) +/* + * Override the weak default implementation and return the + * last PCIe slot number (max number - 1). + */ +int board_pcie_last(void) { - u32 pvr = get_pvr(); - /* * 405EXr only has one EMAC interface, 405EX has two */ - if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) - return 1; + if (is_405exr()) + return 1 - 1; else - return 2; + return 2 - 1; } int checkboard (void) { - char *s = getenv("serial#"); - u32 pvr = get_pvr(); + char buf[64]; + int i = getenv_f("serial#", buf, sizeof(buf)); - if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + if (is_405exr()) printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); else printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); - if (s != NULL) { + if (i > 0) { puts(", serial# "); - puts(s); + puts(buf); } - putc('\n'); + printf(" (CPLD rev. %ld)\n", gd->board_type); return (0); } - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - return 0; -} -#endif /* defined(CONFIG_PCI) */ - -#ifdef CONFIG_PCI -static struct pci_controller pcie_hose[2] = {{0},{0}}; - -void pcie_setup_hoses(int busno) -{ - struct pci_controller *hose; - int i, bus; - int ret = 0; - bus = busno; - char *env; - unsigned int delay; - - for (i = 0; i < board_pcie_count(); i++) { - - if (is_end_point(i)) - ret = ppc4xx_init_pcie_endport(i); - else - ret = ppc4xx_init_pcie_rootport(i); - if (ret) { - printf("PCIE%d: initialization as %s failed\n", i, - is_end_point(i) ? "endpoint" : "root-complex"); - continue; - } - - hose = &pcie_hose[i]; - hose->first_busno = bus; - hose->last_busno = bus; - hose->current_busno = bus; - - /* setup mem resource */ - pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, - PCI_REGION_MEM); - hose->region_count = 1; - pci_register_hose(hose); - - if (is_end_point(i)) { - ppc4xx_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ - } else { - ppc4xx_setup_pcie_rootpoint(hose, i); - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul(env, NULL, 10); - if (delay > 5) - printf("Warning, expect noticable delay before " - "PCIe scan due to 'pciscandelay' value!\n"); - mdelay(delay * 1000); - } - - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; - } - } -} -#endif - -#if defined(CONFIG_POST) -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} -#endif /* CONFIG_POST */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[4]; - int rc; - - ft_cpu_setup(blob, bd); - - /* Fixup NOR mapping */ - val[0] = 0; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize; - rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", - val, sizeof(val), 1); - if (rc) - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */