X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Famcc%2Fluan%2Fluan.c;h=5f76672fb522a04e77c34a6710ed98ef908d6271;hb=1d96cfe8f5eebfc6ea39d1a387f35ca4499e6b67;hp=de3e3d8b925d36a8cfaa8b1e53a6ce1e0ea3968e;hpb=cb5473205206c7f14cbb1e747f28ec75b48826e2;p=u-boot

diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index de3e3d8b92..5f76672fb5 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -42,34 +42,34 @@ int board_early_init_f(void)
 {
 	u32 mfr;
 
-	mtebc( pb0ap,  0x03800000 );	/* set chip selects */
-	mtebc( pb0cr,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
-	mtebc( pb1ap,  0x03800000 );
-	mtebc( pb1cr,  0xff018000 );	/* ebc0_b1cr, 1MB at 0xff000000 CS1 */
-	mtebc( pb2ap,  0x03800000 );
-	mtebc( pb2cr,  0xff838000 );	/* ebc0_b2cr, 2MB at 0xff800000 CS2 */
-
-	mtdcr( uic1sr, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( uic1er, 0x00000000 );	/* disable all interrupts */
-	mtdcr( uic1cr, 0x00000000 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( uic1pr, 0x7fff83ff );	/* Set Interrupt Polarities */
-	mtdcr( uic1tr, 0x001f8000 );	/* Set Interrupt Trigger Levels */
-	mtdcr( uic1vr, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( uic1sr, 0x00000000 );	/* clear all interrupts */
-	mtdcr( uic1sr, 0xffffffff );
-
-	mtdcr( uic0sr, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( uic0er, 0x00000000 );	/* disable all interrupts excepted cascade */
-	mtdcr( uic0cr, 0x00000001 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( uic0pr, 0xffffffff );	/* Set Interrupt Polarities */
-	mtdcr( uic0tr, 0x01000004 );	/* Set Interrupt Trigger Levels */
-	mtdcr( uic0vr, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( uic0sr, 0x00000000 );	/* clear all interrupts */
-	mtdcr( uic0sr, 0xffffffff );
-
-	mfsdr(sdr_mfr, mfr);
+	mtebc( PB0AP,  0x03800000 );	/* set chip selects */
+	mtebc( PB0CR,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+	mtebc( PB1AP,  0x03800000 );
+	mtebc( PB1CR,  0xff018000 );	/* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+	mtebc( PB2AP,  0x03800000 );
+	mtebc( PB2CR,  0xff838000 );	/* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+
+	mtdcr( UIC1SR, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( UIC1ER, 0x00000000 );	/* disable all interrupts */
+	mtdcr( UIC1CR, 0x00000000 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( UIC1PR, 0x7fff83ff );	/* Set Interrupt Polarities */
+	mtdcr( UIC1TR, 0x001f8000 );	/* Set Interrupt Trigger Levels */
+	mtdcr( UIC1VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( UIC1SR, 0x00000000 );	/* clear all interrupts */
+	mtdcr( UIC1SR, 0xffffffff );
+
+	mtdcr( UIC0SR, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( UIC0ER, 0x00000000 );	/* disable all interrupts excepted cascade */
+	mtdcr( UIC0CR, 0x00000001 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( UIC0PR, 0xffffffff );	/* Set Interrupt Polarities */
+	mtdcr( UIC0TR, 0x01000004 );	/* Set Interrupt Trigger Levels */
+	mtdcr( UIC0VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( UIC0SR, 0x00000000 );	/* clear all interrupts */
+	mtdcr( UIC0SR, 0xffffffff );
+
+	mfsdr(SDR0_MFR, mfr);
 	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
-	mtsdr(sdr_mfr, mfr);
+	mtsdr(SDR0_MFR, mfr);
 
 	return  0;
 }
@@ -147,7 +147,7 @@ int pci_pre_init( struct pci_controller *hose )
 	 *	The luan board is always configured as the host & requires the
 	 *	PCI arbiter to be enabled.
 	 *--------------------------------------------------------------------------*/
-	mfsdr(sdr_sdstp1, strap);
+	mfsdr(SDR0_SDSTP1, strap);
 	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
 		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 
@@ -319,7 +319,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 			l2cache_status() ? "ON" : "OFF");
 		return 0;
 	default:
-		printf ("Usage:\n%s\n", cmdtp->usage);
+		cmd_usage(cmdtp);
 		return 1;
 	}
 
@@ -329,7 +329,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
 
 U_BOOT_CMD(
 	l2cache,   2,   1,     do_l2cache,
-	"l2cache  - enable or disable L2 cache\n",
+	"enable or disable L2 cache",
 	"[on, off]\n"
-	"    - enable or disable L2 cache\n"
-	);
+	"    - enable or disable L2 cache"
+);