X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Famcc%2Fwalnut%2Fwalnut.c;h=4f299324cd751585f813233e4868543ab5158702;hb=9e2032aa56a722af8959cd214cc1e54d59b2ba64;hp=f1a96a6e7d23a9c90209ccb7caa66d32b74548ef;hpb=77ddac9480d63a80b6bb76d7ee4dcc2d1070867e;p=u-boot

diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index f1a96a6e7d..4f299324cd 100644
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -47,13 +47,13 @@ int board_early_init_f(void)
 	  |
 	  +-------------------------------------------------------------------------*/
 
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(uicer, 0x00000000);	/* disable all ints */
-	mtdcr(uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
-	mtdcr(uicpr, 0xFFFFFFE0);	/* set int polarities */
-	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFFE0);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/* set UART1 control to select CTS/RTS */
 #define FPGA_BRDC       0xF0300004
@@ -85,27 +85,11 @@ int checkboard(void)
 	return (0);
 }
 
-/*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-	return;
-}
-
 /*
  * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
-	return spd_sdram(0);
-}
-
-int testdram(void)
-{
-	/* TODO: XXX XXX XXX */
-	printf("test: xxx MB - ok\n");
-
-	return (0);
+	return spd_sdram();
 }