X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Famcc%2Fyellowstone%2Fyellowstone.c;h=20965c8e3ead7e039b17eb289f5e864af425e6ea;hb=b86d7622b33892b1dafe761a7a9eaeeab9f3816b;hp=c2b7cf17737c5af25c687468e3ef6877b5e1d3f4;hpb=e190290ba40fc5340cefd04dd6abf5def15065b9;p=u-boot

diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index c2b7cf1773..20965c8e3e 100644
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -24,6 +24,8 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 int board_early_init_f(void)
@@ -55,33 +57,14 @@ int board_early_init_f(void)
 	mtebc(pb5ap, 0x00000000);
 	mtebc(pb5cr, 0x00000000);
 
-	/*--------------------------------------------------------------------
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-
 	/*--------------------------------------------------------------------
 	 * Setup the GPIO pins
 	 *-------------------------------------------------------------------*/
 	/*CPLD cs */
-	/*setup Address lines for flash sizes larger than 16Meg. */
-	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
+	/*setup Address lines for flash size 64Meg. */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
 
 	/*setup emac */
 	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
@@ -109,6 +92,25 @@ int board_early_init_f(void)
 	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
 #endif
 
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
 	/*--------------------------------------------------------------------
 	 * Setup other serial configuration
 	 *-------------------------------------------------------------------*/
@@ -129,14 +131,13 @@ int board_early_init_f(void)
 #endif
 
 	/*get rid of flash write protect */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
+	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
 
 	return 0;
 }
 
 int misc_init_r (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	uint pbcr;
 	int size_val = 0;
 
@@ -173,6 +174,10 @@ int misc_init_r (void)
 	mtdcr(ebccfga, pb0cr);
 	mtdcr(ebccfgd, pbcr);
 
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
 			    -CFG_MONITOR_LEN,
@@ -184,10 +189,7 @@ int misc_init_r (void)
 
 int checkboard(void)
 {
-	sys_info_t sysinfo;
-	unsigned char *s = getenv("serial#");
-
-	get_sys_info(&sysinfo);
+	char *s = getenv("serial#");
 
 	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 	if (s != NULL) {
@@ -196,13 +198,6 @@ int checkboard(void)
 	}
 	putc('\n');
 
-	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
-	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
-	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
-	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
-	printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-	printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
-
 	return (0);
 }
 
@@ -213,9 +208,85 @@ int checkboard(void)
  *              PLB @ 133 MHz
  *
  ************************************************************************/
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+	int i;
+	int j, k;
+	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
+	int first_good = -1, last_bad = 0x1ff;
+
+	unsigned long test[NUM_TRIES] = {
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+	/* go through all possible SDRAM0_TR1[RDCT] values */
+	for (i=0; i<=0x1ff; i++) {
+		/* set the current value for TR1 */
+		mtsdram(mem_tr1, (0x80800800 | i));
+
+		/* write values */
+		for (j=0; j<NUM_TRIES; j++) {
+			ram_pointer[j] = test[j];
+
+			/* clear any cache at ram location */
+			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+		}
+
+		/* read values back */
+		for (j=0; j<NUM_TRIES; j++) {
+			for (k=0; k<NUM_READS; k++) {
+				/* clear any cache at ram location */
+				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+				if (ram_pointer[j] != test[j])
+					break;
+			}
+
+			/* read error */
+			if (k != NUM_READS) {
+				break;
+			}
+		}
+
+		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
+		if (j == NUM_TRIES) {
+			if (first_good == -1)
+				first_good = i;		/* found beginning of window */
+		} else { /* bad read */
+			/* if we have not had a good read then don't care */
+			if(first_good != -1) {
+				/* first failure after a good read */
+				last_bad = i-1;
+				break;
+			}
+		}
+	}
+
+	/* return the current value for TR1 */
+	*tr1_value = (first_good + last_bad) / 2;
+}
+
 void sdram_init(void)
 {
 	register uint reg;
+	int tr1_bank1, tr1_bank2;
 
 	/*--------------------------------------------------------------------
 	 * Setup some default
@@ -227,7 +298,7 @@ void sdram_init(void)
 	mtsdram(mem_wddctr, 0x40000000);	/* ?? */
 
 	/*clear this first, if the DDR is enabled by a debugger
-	   then you can not make changes. */
+	  then you can not make changes. */
 	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */
 
 	/*--------------------------------------------------------------------
@@ -240,7 +311,6 @@ void sdram_init(void)
 	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
 
 	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
-	mtsdram(mem_tr1, 0x8080080b);	/* ?? */
 	mtsdram(mem_rtr, 0x04080000);	/* ?? */
 	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
 	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
@@ -256,6 +326,10 @@ void sdram_init(void)
 		if (reg & 0x80000000)
 			break;
 	}
+
+	sdram_tr1_set(0x00000000, &tr1_bank1);
+	sdram_tr1_set(0x08000000, &tr1_bank2);
+	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
 }
 
 /*************************************************************************
@@ -321,20 +395,8 @@ int testdram(void)
 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 int pci_pre_init(struct pci_controller *hose)
 {
-	unsigned long strap;
 	unsigned long addr;
 
-	/*--------------------------------------------------------------------------+
-	 *	Bamboo is always configured as the host & requires the
-	 *	PCI arbiter to be enabled.
-	 *--------------------------------------------------------------------------*/
-	mfsdr(sdr_sdstp1, strap);
-	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
-		printf("PCI: SDR0_STRP1[PAE] not set.\n");
-		printf("PCI: Configuration aborted.\n");
-		return 0;
-	}
-
 	/*-------------------------------------------------------------------------+
 	  | Set priority for all PLB3 devices to 0.
 	  | Set PLB3 arbiter to fair mode.