X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Famcc%2Fyosemite%2Fyosemite.c;h=56b5191d6667187467e6b6ba789577b63891b6f3;hb=08aa0334c6e885491c6d10fa4a8209b8917fbf63;hp=2a654fa895ba8989df09f47eea2640c20f83a57f;hpb=d1c3b27525b664e8c4db6bb173eed51bfc8220de;p=u-boot diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 2a654fa895..56b5191d66 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -2,27 +2,11 @@ * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include -#include +#include #include #include #include @@ -33,6 +17,15 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +static inline u32 get_async_pci_freq(void) +{ + if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & + CONFIG_SYS_BCSR5_PCI66EN) + return 66666666; + else + return 33333333; +} + int board_early_init_f(void) { register uint reg; @@ -82,21 +75,21 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ + mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup other serial configuration @@ -106,6 +99,9 @@ int board_early_init_f(void) mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ + /* Check and reconfigure the PCI sync clock if necessary */ + ppc4xx_pci_sync_clock_config(get_async_pci_freq()); + /*clear tmrclk divisor */ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00; @@ -176,9 +172,10 @@ int misc_init_r (void) int checkboard(void) { - char *s = getenv("serial#"); + char buf[64]; + int i = getenv_f("serial#", buf, sizeof(buf)); u8 rev; - u8 val; + u32 clock = get_async_pci_freq(); #ifdef CONFIG_440EP printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); @@ -187,15 +184,23 @@ int checkboard(void) #endif rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN; - printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); - if (s != NULL) { + if (i > 0) { puts(", serial# "); - puts(s); + puts(buf); } putc('\n'); + /* + * Reconfiguration of the PCI sync clock is already done, + * now check again if everything is in range: + */ + if (ppc4xx_pci_sync_clock_config(clock)) { + printf("ERROR: PCI clocking incorrect (async=%d " + "sync=%ld)!\n", clock, get_PCI_freq()); + } + return (0); } @@ -237,7 +242,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) /* go through all possible SDRAM0_TR1[RDCT] values */ for (i=0; i<=0x1ff; i++) { /* set the current value for TR1 */ - mtsdram(mem_tr1, (0x80800800 | i)); + mtsdram(SDRAM0_TR1, (0x80800800 | i)); /* write values */ for (j=0; j PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* Bamboo is always configured as host. */ - return (1); -} -#endif /* defined(CONFIG_PCI) */ - /************************************************************************* * hw_watchdog_reset *