X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fatmel%2Fat91cap9adk%2Fat91cap9adk.c;h=a3eaf1922412a7e603b852417257367c615fe2d8;hb=3070a9a3cb41ed6b19f79590f7713d5685ab1066;hp=bde6aa97f6473062a4be1fbe1985267e7d9ff3b0;hpb=64e8a06af68cda174a8a06d0a61fce5e5bb189d7;p=u-boot diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index bde6aa97f6..a3eaf19224 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop leadtechdesign.com> + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this @@ -23,7 +23,18 @@ */ #include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include +#endif #define MP_BLOCK_3_BASE 0xFDF00000 @@ -37,126 +48,138 @@ DECLARE_GLOBAL_DATA_PTR; static void at91cap9_serial_hw_init(void) { #ifdef CONFIG_USART0 - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0; + at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); #endif #ifdef CONFIG_USART1 - AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1; + at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); #endif #ifdef CONFIG_USART2 - AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2; + at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); #endif #ifdef CONFIG_USART3 /* DBGU */ - AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; + at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); #endif +} - +static void at91cap9_slowclock_hw_init(void) +{ + /* + * On AT91CAP9 revC CPUs, the slow clock can be based on an + * internal impreciseRC oscillator or an external 32kHz oscillator. + * Switch to the latter. + */ +#define ARCH_ID_AT91CAP9_REVB 0x399 +#define ARCH_ID_AT91CAP9_REVC 0x601 + if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) { + unsigned i, tmp = at91_sys_read(AT91_SCKCR); + if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) { + extern void timer_init(void); + timer_init(); + tmp |= AT91CAP9_SCKCR_OSC32EN; + at91_sys_write(AT91_SCKCR, tmp); + for (i = 0; i < 1200; i++) + udelay(1000); + tmp |= AT91CAP9_SCKCR_OSCSEL_32; + at91_sys_write(AT91_SCKCR, tmp); + udelay(200); + tmp &= ~AT91CAP9_SCKCR_RCEN; + at91_sys_write(AT91_SCKCR, tmp); + } + } } static void at91cap9_nor_hw_init(void) { - /* Ensure EBI supply is 3.3V */ - AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3; + unsigned long csa; + /* Ensure EBI supply is 3.3V */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); /* Configure SMC CS0 for parallel flash */ - AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP | - AT91C_FLASH_NCS_WR_SETUP | - AT91C_FLASH_NRD_SETUP | - AT91C_FLASH_NCS_RD_SETUP; - - AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE | - AT91C_FLASH_NCS_WR_PULSE | - AT91C_FLASH_NRD_PULSE | - AT91C_FLASH_NCS_RD_PULSE; - - AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE | - AT91C_FLASH_NRD_CYCLE; - - AT91C_BASE_SMC->SMC_CTRL0 = AT91C_SMC_READMODE | - AT91C_SMC_WRITEMODE | - AT91C_SMC_NWAITM_NWAIT_DISABLE | - AT91C_SMC_BAT_BYTE_WRITE | - AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | - (AT91C_SMC_TDF & (1 << 16)); + at91_sys_write(AT91_SMC_SETUP(0), + AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) | + AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2)); + at91_sys_write(AT91_SMC_PULSE(0), + AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) | + AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10)); + at91_sys_write(AT91_SMC_CYCLE(0), + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); + at91_sys_write(AT91_SMC_MODE(0), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | + AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); } #ifdef CONFIG_CMD_NAND static void at91cap9_nand_hw_init(void) { + unsigned long csa; + /* Enable CS3 */ - AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3; + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | + AT91_MATRIX_EBI_VDDIOMSEL_3_3V); /* Configure SMC CS3 for NAND/SmartMedia */ - AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP | - AT91C_SM_NCS_WR_SETUP | - AT91C_SM_NRD_SETUP | - AT91C_SM_NCS_RD_SETUP; - - AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE | - AT91C_SM_NCS_WR_PULSE | - AT91C_SM_NRD_PULSE | - AT91C_SM_NCS_RD_PULSE; - - AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE | - AT91C_SM_NRD_CYCLE; - - AT91C_BASE_SMC->SMC_CTRL3 = AT91C_SMC_READMODE | - AT91C_SMC_WRITEMODE | - AT91C_SMC_NWAITM_NWAIT_DISABLE | - AT91C_SMC_DBW_WIDTH_EIGTH_BITS | - AT91C_SM_TDF; + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) | + AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) | + AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(1)); - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD; + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD); /* RDY/BSY is not connected */ /* Enable NandFlash */ - AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15; - AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15; + at91_set_gpio_output(AT91_PIN_PD15, 1); } #endif #ifdef CONFIG_HAS_DATAFLASH static void at91cap9_spi_hw_init(void) { - AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D | - AT91C_PD1_SPI0_NPCS3D; - AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D | - AT91C_PD1_SPI0_NPCS3D; - - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A; - AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A | - AT91C_PA1_SPI0_MOSI | - AT91C_PA0_SPI0_MISO | - AT91C_PA3_SPI0_NPCS1 | - AT91C_PA5_SPI0_NPCS0 | - AT91C_PA2_SPI0_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A | - AT91C_PA4_SPI0_NPCS2A | - AT91C_PA1_SPI0_MOSI | - AT91C_PA0_SPI0_MISO | - AT91C_PA3_SPI0_NPCS1 | - AT91C_PA5_SPI0_NPCS0 | - AT91C_PA2_SPI0_SPCK; - - /* Enable Clock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0; + at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */ + + at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0); } #endif #ifdef CONFIG_MACB static void at91cap9_macb_hw_init(void) { - unsigned int gpio; - /* Enable clock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC); /* * Disable pull-up on: @@ -166,54 +189,59 @@ static void at91cap9_macb_hw_init(void) * * PHY has internal pull-down */ - AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV | - AT91C_PB25_E_RX0 | - AT91C_PB26_E_RX1; + writel(pin_to_mask(AT91_PIN_PB22) | + pin_to_mask(AT91_PIN_PB25) | + pin_to_mask(AT91_PIN_PB26), + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); /* Need to reset PHY -> 500ms reset */ - AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) | - (AT91C_RSTC_ERSTL & (0x0D << 8)) | - AT91C_RSTC_URSTEN; - AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) | - AT91C_RSTC_EXTRST; + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + AT91_RSTC_ERSTL | (0x0D << 8) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); /* Wait for end hardware reset */ - while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)); + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); /* Re-enable pull-up */ - AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV | - AT91C_PB25_E_RX0 | - AT91C_PB26_E_RX1; - -#ifdef CONFIG_RMII - gpio = AT91C_PB30_E_MDIO | - AT91C_PB29_E_MDC | - AT91C_PB21_E_TXCK | - AT91C_PB27_E_RXER | - AT91C_PB25_E_RX0 | - AT91C_PB22_E_RXDV | - AT91C_PB26_E_RX1 | - AT91C_PB28_E_TXEN | - AT91C_PB23_E_TX0 | - AT91C_PB24_E_TX1; - AT91C_BASE_PIOB->PIO_ASR = gpio; - AT91C_BASE_PIOB->PIO_BSR = 0; - AT91C_BASE_PIOB->PIO_PDR = gpio; -#else -#error AT91CAP9A-DK works only in RMII mode + writel(pin_to_mask(AT91_PIN_PB22) | + pin_to_mask(AT91_PIN_PB25) | + pin_to_mask(AT91_PIN_PB26), + pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + + at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ #endif - /* Unlock EMAC, 3 0 2 1 sequence */ #define MP_MAC_KEY0 0x5969cb2a #define MP_MAC_KEY1 0xb4a1872e #define MP_MAC_KEY2 0x05683fbc #define MP_MAC_KEY3 0x3634fba4 #define UNLOCK_MAC 0x00000008 - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC; + writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c); + writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30); + writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38); + writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34); + writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40); } #endif @@ -226,11 +254,70 @@ static void at91cap9_uhp_hw_init(void) #define MP_OHCI_KEY2 0x4823efbc #define MP_OHCI_KEY3 0x8651aae4 #define UNLOCK_OHCI 0x00000010 - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1; - *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI; + writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c); + writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38); + writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30); + writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34); + writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91CAP9_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */ +} + +static void at91cap9_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC); + + gd->fb_base = 0; } #endif @@ -245,6 +332,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; at91cap9_serial_hw_init(); + at91cap9_slowclock_hw_init(); at91cap9_nor_hw_init(); #ifdef CONFIG_CMD_NAND at91cap9_nand_hw_init(); @@ -258,7 +346,9 @@ int board_init(void) #ifdef CONFIG_USB_OHCI_NEW at91cap9_uhp_hw_init(); #endif - +#ifdef CONFIG_LCD + at91cap9_lcd_hw_init(); +#endif return 0; }