X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fatmel%2Fat91sam9261ek%2Fat91sam9261ek.c;h=6f15bc677671a3b9d80321c6f0a2206573d87219;hb=8fad5e0b114fdd4c4e8d5f105ea3527df2c83986;hp=2f6b599a6ba08e462c56f7495e952f859661de4c;hpb=bb272ec8df6e35b7e19ce1237cae28798167a624;p=u-boot diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 2f6b599a6b..6f15bc6776 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -1,43 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ #include +#include +#include #include #include #include #include -#include #include #include #include -#include #include #include #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) #include #include #endif +#include DECLARE_GLOBAL_DATA_PTR; @@ -49,44 +33,47 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND static void at91sam9261ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ #ifdef CONFIG_AT91SAM9G10EK - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); #else - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); #endif - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -102,35 +89,37 @@ static void at91sam9261ek_nand_hw_init(void) #ifdef CONFIG_DRIVER_DM9000 static void at91sam9261ek_dm9000_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + /* Configure SMC CS2 for DM9000 */ #ifdef CONFIG_AT91SAM9G10EK - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); #else - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); #endif /* Configure Reset signal as output */ @@ -143,20 +132,20 @@ static void at91sam9261ek_dm9000_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: AT91SAM9261_LCDC_BASE, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -194,12 +183,11 @@ static void at91sam9261ek_lcd_hw_init(void) at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + at91_system_clk_enable(AT91_PMC_HCK1); -#ifdef CONFIG_AT91SAM9G10EK - gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE; -#else - gd->fb_base = AT91SAM9261_SRAM_BASE; + /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */ +#ifdef CONFIG_AT91SAM9261EK + gd->fb_base = ATMEL_BASE_SRAM; #endif } @@ -217,7 +205,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -225,7 +213,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += get_nand_dev_by_index(i)->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); @@ -233,11 +221,25 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif -int board_init(void) +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) { - /* Enable Ctrlc */ - console_init_f(); + at91_seriald_hw_init(); +} +#endif +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ #ifdef CONFIG_AT91SAM9G10EK /* arch number of AT91SAM9G10EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK; @@ -246,15 +248,11 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9261ek_nand_hw_init(); #endif -#ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); -#endif #ifdef CONFIG_DRIVER_DM9000 at91sam9261ek_dm9000_hw_init(); #endif @@ -265,15 +263,17 @@ int board_init(void) } #ifdef CONFIG_DRIVER_DM9000 - int board_eth_init(bd_t *bis) - { +int board_eth_init(bd_t *bis) +{ return dm9000_initialize(bis); - } - #endif +} +#endif + int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; } @@ -285,7 +285,7 @@ void reset_phy(void) * Initialize ethernet HW addr prior to starting Linux, * needed for nfsroot */ - eth_init(gd->bd); + eth_init(); #endif } #endif