X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fatmel%2Fsama5d3xek%2Fsama5d3xek.c;h=cae6e245ddbc90e28b76f7f179f4f8f12817a844;hb=99b47c25d0e2bdc9ebbd685a87456e175581c695;hp=eff94a48b22b12fb6f6c8e0f29d7deb8a6c70315;hpb=a891601ce51edbafa1a2750c96a618e4fcbca1c2;p=u-boot

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index eff94a48b2..cae6e245dd 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -6,28 +6,22 @@
  */
 
 #include <common.h>
-#include <mmc.h>
 #include <asm/io.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
+#include <debug_uart.h>
 #include <lcd.h>
-#include <atmel_lcdc.h>
-#include <atmel_mci.h>
+#include <linux/ctype.h>
+#include <atmel_hlcdc.h>
+#include <phy.h>
 #include <micrel.h>
-#include <net.h>
-#include <netdev.h>
 #include <spl.h>
 #include <asm/arch/atmel_mpddrc.h>
 #include <asm/arch/at91_wdt.h>
 
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-#include <asm/arch/atmel_usba_udc.h>
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
@@ -67,6 +61,61 @@ void sama5d3xek_nand_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_MTD_NOR_FLASH
+static void sama5d3xek_nor_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+	at91_periph_clk_enable(ATMEL_ID_SMC);
+
+	/* Configure SMC CS0 for NOR flash */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
+	       AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
+	       &smc->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
+	       &smc->cs[0].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
+	       AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
+	       AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
+	       AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_16 |
+	       AT91_SMC_MODE_TDF_CYCLE(1),
+	       &smc->cs[0].mode);
+
+	/* Address pin (A1 ~ A23) configuration */
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
+	/* CS0 pin configuration */
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
+}
+#endif
+
 #ifdef CONFIG_CMD_USB
 static void sama5d3xek_usb_hw_init(void)
 {
@@ -79,8 +128,6 @@ static void sama5d3xek_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 static void sama5d3xek_mci_hw_init(void)
 {
-	at91_mci_hw_init();
-
 	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
 }
 #endif
@@ -90,7 +137,6 @@ vidinfo_t panel_info = {
 	.vl_col = 800,
 	.vl_row = 480,
 	.vl_clk = 24000000,
-	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
 	.vl_bpix = LCD_BPP,
 	.vl_tft = 1,
 	.vl_hsync_len = 128,
@@ -115,14 +161,14 @@ static void sama5d3xek_lcd_hw_init(void)
 	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
 
 	/* The higher 8 bit of LCD is board related */
-	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
-	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
-	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
-	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
-	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
-	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
-	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
-	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */
 
 	/* Configure lower 16 bit of LCD and enable clock */
 	at91_lcd_hw_init();
@@ -152,7 +198,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
@@ -160,18 +206,22 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
 	at91_seriald_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -181,24 +231,15 @@ int board_init(void)
 #ifdef CONFIG_NAND_ATMEL
 	sama5d3xek_nand_hw_init();
 #endif
+#ifdef CONFIG_MTD_NOR_FLASH
+	sama5d3xek_nor_hw_init();
+#endif
 #ifdef CONFIG_CMD_USB
 	sama5d3xek_usb_hw_init();
 #endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	at91_udp_hw_init();
-#endif
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 	sama5d3xek_mci_hw_init();
 #endif
-#ifdef CONFIG_ATMEL_SPI
-	at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
-	if (has_emac())
-		at91_macb_hw_init();
-	if (has_gmac())
-		at91_gmac_hw_init();
-#endif
 #ifdef CONFIG_LCD
 	if (has_lcdc())
 		sama5d3xek_lcd_hw_init();
@@ -213,104 +254,35 @@ int dram_init(void)
 	return 0;
 }
 
-int board_phy_config(struct phy_device *phydev)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
 {
-	/* rx data delay */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
-	/* tx data delay */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
-	/* rx/tx clock delay */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
-
-	return 0;
-}
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	const int MAX_STR_LEN = 32;
+	char name[MAX_STR_LEN], *p;
+	int i;
 
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
+	strncpy(name, get_cpu_name(), MAX_STR_LEN);
+	for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
+		*p = tolower(*p);
 
-#ifdef CONFIG_MACB
-	if (has_emac())
-		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-	if (has_gmac())
-		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	strcat(name, "ek.dtb");
+	setenv("dtb_name", name);
 #endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
-	usb_eth_initialize(bis);
-#endif
-#endif
-
-	return rc;
-}
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-	int rc = 0;
-
-	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
-	return rc;
+	return 0;
 }
 #endif
 
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs < 4;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	switch (slave->cs) {
-	case 0:
-		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
-	case 2:
-		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
-	case 3:
-		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
-	default:
-		break;
-	}
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	switch (slave->cs) {
-	case 0:
-		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
-	case 2:
-		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
-	case 3:
-		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
-	default:
-		break;
-	}
-}
-#endif /* CONFIG_ATMEL_SPI */
-
 /* SPL */
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_MMC
-	sama5d3xek_mci_hw_init();
+#if CONFIG_SYS_USE_NANDFLASH
+	sama5d3xek_nand_hw_init();
 #endif
 }
 
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 {
 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 
@@ -351,22 +323,20 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	struct atmel_mpddr ddr2;
+	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable MPDDR clock */
+	/* Enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(0x4, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_DDR);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 }
 
 void at91_pmc_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	u32 tmp;
 
 	tmp = AT91_PMC_PLLAR_29 |
@@ -375,7 +345,7 @@ void at91_pmc_init(void)
 	      AT91_PMC_PLLXR_DIV(1);
 	at91_plla_init(tmp);
 
-	writel(0x3 << 8, &pmc->pllicpr);
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
 
 	tmp = AT91_PMC_MCKR_MDIV_4 |
 	      AT91_PMC_MCKR_CSS_PLLA;