X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fatum8548%2Fatum8548.c;h=9403e4b02fda4f9b673d49f5ca909e0873c62181;hb=739192b4252352235b499388ba9974b695b0a9b1;hp=7a02cdc5b980e412f137c3918f3f8826e075ab6e;hpb=fb3143b35eb5890ec72e79d17a6068a84a057d47;p=u-boot

diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index 7a02cdc5b9..9403e4b02f 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -47,7 +47,7 @@ int board_early_init_f (void)
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
@@ -170,182 +170,112 @@ static struct pci_controller pci2_hose;
 static struct pci_controller pcie1_hose;
 #endif
 
-int first_free_busno=0;
-
-void
-pci_init_board(void)
+void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info[3];
+	u32 devdisr, pordevsr, io_sel;
+	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+	int first_free_busno = 0;
+	int num = 0;
+
+	int pcie_ep, pcie_configured;
 
-	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 
-	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
-		devdisr, io_sel, host_agent);
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
 	/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
-	gur->clkocr  |= MPC85xx_ATUM_CLKOCR;
+	setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR);
 
 	if (io_sel & 1) {
 		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
-			printf ("    eTSEC1 is in sgmii mode.\n");
+			printf("eTSEC1 is in sgmii mode.\n");
 		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
-			printf ("    eTSEC2 is in sgmii mode.\n");
+			printf("eTSEC2 is in sgmii mode.\n");
 		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
-			printf ("    eTSEC3 is in sgmii mode.\n");
+			printf("eTSEC3 is in sgmii mode.\n");
 		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
-			printf ("    eTSEC4 is in sgmii mode.\n");
+			printf("eTSEC4 is in sgmii mode.\n");
 	}
 
 #ifdef CONFIG_PCIE1
- {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pcie1_hose;
-	int pcie_ep = (host_agent == 5);
-	int pcie_configured  = io_sel & 6;
-	struct pci_region *r = hose->regions;
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		printf ("\n    PCIE1 connected to slot as %s (base address %x)",
-			pcie_ep ? "End Point" : "Root Complex",
-			(uint)pci);
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
-		}
-		printf ("\n");
-
-		/* inbound */
-		r += fsl_pci_setup_inbound_windows(r);
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
-			       CONFIG_SYS_PCIE1_MEM_PHYS,
-			       CONFIG_SYS_PCIE1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BASE,
-			       CONFIG_SYS_PCIE1_IO_PHYS,
-			       CONFIG_SYS_PCIE1_IO_SIZE,
-			       PCI_REGION_IO);
-
-#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
 		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE2,
+		pci_set_region(&pcie1_hose.regions[0],
+			       CONFIG_SYS_PCIE1_MEM_BUS2,
 			       CONFIG_SYS_PCIE1_MEM_PHYS2,
 			       CONFIG_SYS_PCIE1_MEM_SIZE2,
 			       PCI_REGION_MEM);
-#endif
-		hose->region_count = r - hose->regions;
-		hose->first_busno=first_free_busno;
 
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		first_free_busno=hose->last_busno+1;
-		printf("    PCIE1 on bus %02x - %02x\n",
-		       hose->first_busno,hose->last_busno);
+		pcie1_hose.region_count = 1;
+#endif
+		printf ("PCIE1: connected to Slot as %s (base addr %lx)\n",
+				pcie_ep ? "Endpoint" : "Root Complex",
+				pci_info[num].regs);
 
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
 	} else {
-		printf ("    PCIE1: disabled\n");
+		printf("PCIE1: disabled\n");
 	}
 
- }
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 #endif
 
 #ifdef CONFIG_PCI1
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-	struct pci_controller *hose = &pci1_hose;
-	struct pci_region *r = hose->regions;
-
-	uint pci_agent = (host_agent == 6);
-	uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
-	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
-	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
-	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */
+	pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
+	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
+	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		printf ("\n    PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+		SET_STD_PCI_INFO(pci_info[num], 1);
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
 			(pci_speed == 66666000) ? "66" : "unknown",
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
-			(uint)pci
-			);
+			pci_info[num].regs);
 
-		/* inbound */
-		r += fsl_pci_setup_inbound_windows(r);
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
-			       CONFIG_SYS_PCI1_MEM_PHYS,
-			       CONFIG_SYS_PCI1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BASE,
-			       CONFIG_SYS_PCI1_IO_PHYS,
-			       CONFIG_SYS_PCI1_IO_SIZE,
-			       PCI_REGION_IO);
-		hose->region_count = r - hose->regions;
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		first_free_busno=hose->last_busno+1;
-		printf ("PCI1 on bus %02x - %02x\n",
-			hose->first_busno,hose->last_busno);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pci1_hose, first_free_busno);
 	} else {
-		printf ("    PCI1: disabled\n");
+		printf("PCI1: disabled\n");
 	}
-}
+
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 #endif
 
 #ifdef CONFIG_PCI2
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
-	struct pci_controller *hose = &pci2_hose;
-	struct pci_region *r = hose->regions;
-
 	if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
-		r += fsl_pci_setup_inbound_windows(r);
-
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI2_MEM_BASE,
-			       CONFIG_SYS_PCI2_MEM_PHYS,
-			       CONFIG_SYS_PCI2_MEM_SIZE,
-			       PCI_REGION_MEM);
+		SET_STD_PCI_INFO(pci_info[num], 2);
+		pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
 
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI2_IO_BASE,
-			       CONFIG_SYS_PCI2_IO_PHYS,
-			       CONFIG_SYS_PCI2_IO_SIZE,
-			       PCI_REGION_IO);
-		hose->region_count = r - hose->regions;
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		first_free_busno=hose->last_busno+1;
-		printf ("PCI2 on bus %02x - %02x\n",
-			hose->first_busno,hose->last_busno);
+		puts("PCI2\n");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pci1_hose, first_free_busno);
 	} else {
-		printf ("    PCI2: disabled\n");
+		printf("PCI2: disabled\n");
 	}
-}
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCI2;
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
 #endif
 }
 
@@ -362,14 +292,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCI2
-	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+	FT_FSL_PCI_SETUP;
 }
 #endif