X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fbf548-ezkit%2Fbf548-ezkit.c;h=31d6eeec0cef7beb3fcd60d2052b0aa16155b4d8;hb=7233fb3143c7329cb072318ce39360213d80ea54;hp=88a0cd4d619b9d15ddc9ebaf1615fd76199bc4da;hpb=4fb799aeafa71c4e6caacd3acdc4a4547cfbd5d4;p=u-boot

diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c
index 88a0cd4d61..31d6eeec0c 100644
--- a/board/bf548-ezkit/bf548-ezkit.c
+++ b/board/bf548-ezkit/bf548-ezkit.c
@@ -1,5 +1,5 @@
 /*
- * U-boot - main board file
+ * U-Boot - main board file
  *
  * Copyright (c) 2005-2008 Analog Devices Inc.
  *
@@ -7,10 +7,13 @@
  */
 
 #include <common.h>
-#include <netdev.h>
 #include <config.h>
 #include <command.h>
+#include <netdev.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/sdh.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -21,62 +24,15 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
-	return gd->bd->bi_memsize;
-}
-
 int board_early_init_f(void)
 {
-	/* Port H: PH8 - PH13 == A4 - A9
-	 * address lines of the parallel asynchronous memory interface
-	 */
-
-	/************************************************
-	* configure GPIO 				*
-	* set port H function enable register		*
-	*  configure PH8-PH13 as peripheral (not GPIO) 	*
-	*************************************************/
-	bfin_write_PORTH_FER(0x3F03);
-
-	/************************************************
-	* set port H MUX to configure PH8-PH13		*
-	*  1st Function (MUX = 00) (bits 16-27 == 0)	*
-	*  Set to address signals A4-A9 		*
-	*************************************************/
-	bfin_write_PORTH_MUX(0);
-
-	/************************************************
-	* set port H direction register			*
-	*  enable PH8-PH13 as outputs			*
-	*************************************************/
-	bfin_write_PORTH_DIR_SET(0x3F00);
-
-	/* Port I: PI0 - PH14 == A10 - A24
-	 * address lines of the parallel asynchronous memory interface
-	 */
-
-	/************************************************
-	* set port I function enable register		*
-	*  configure PI0-PI14 as peripheral (not GPIO) 	*
-	*************************************************/
-	bfin_write_PORTI_FER(0x7fff);
-
-	/**************************************************
-	* set PORT I MUX to configure PI14-PI0 as	  *
-	* 1st Function (MUX=00) - address signals A10-A24 *
-	***************************************************/
-	bfin_write_PORTI_MUX(0);
-
-	/****************************************
-	* set PORT I direction register		*
-	*  enable PI0 - PI14 as outputs		*
-	*****************************************/
-	bfin_write_PORTI_DIR_SET(0x7fff);
-
-	return 0;
+	/* Set async addr lines as peripheral */
+	const unsigned short pins[] = {
+		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+		P_A21, P_A22, P_A23, P_A24, 0
+	};
+	return peripheral_request_list(pins, "async");
 }
 
 #ifdef CONFIG_SMC911X
@@ -85,3 +41,24 @@ int board_eth_init(bd_t *bis)
 	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 }
 #endif
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+	return bfin_mmc_init(bis);
+}
+#endif
+
+#ifdef CONFIG_USB_BLACKFIN
+void board_musb_init(void)
+{
+	/*
+	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
+	 * and OTG host modes, while rev 1.1 and greater require PE7 to
+	 * be low for device mode and high for host mode.  We set it high
+	 * here because we are in host mode.
+	 */
+	gpio_request(GPIO_PE7, "musb-vbus");
+	gpio_direction_output(GPIO_PE7, 1);
+}
+#endif