X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcanmb%2Fcanmb.c;h=6c3d2acfd29a4d14c2432413788628d6c7eb50d2;hb=8603b69b8b04e3e34f8744b396c62833b78fd7c1;hp=1782b314f88d71a833f623d892b0eb8eca0cc75a;hpb=07cc0999413481568b38b8d0e5f3d7514d9540b0;p=u-boot

diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
index 1782b314f8..6c3d2acfd2 100644
--- a/board/canmb/canmb.c
+++ b/board/canmb/canmb.c
@@ -34,7 +34,7 @@
 #include "mt48lc16m32s2-75.h"
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -77,16 +77,15 @@ static void sdram_start (int hi_addr)
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -107,9 +106,9 @@ long int initdram (int board_type)
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -135,10 +134,10 @@ long int initdram (int board_type)
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -160,7 +159,7 @@ long int initdram (int board_type)
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -178,62 +177,11 @@ long int initdram (int board_type)
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize + dramsize2;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-long int initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CFG_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CFG_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
 	puts ("Board: CANMB\n");
@@ -244,8 +192,8 @@ int board_early_init_r (void)
 {
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 	*(vu_long *)MPC5XXX_BOOTCS_START =
-	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
 	*(vu_long *)MPC5XXX_BOOTCS_STOP =
-	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
 	return 0;
 }