X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcm_t35%2Fcm_t35.c;h=edbb941985c103e8d18ab2069471f7bd6ef95fa2;hb=4a207e8b9a1ecc3e87d5a63bb5442dbcd50bd4b6;hp=ff372d836fe382226ace709b8597798bf0a4695f;hpb=ce15ec9f695c5ee7023c3e256ee67a2538496c46;p=u-boot diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index ff372d836f..edbb941985 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -32,7 +32,9 @@ #include #include #include +#include #include +#include #include #include @@ -40,6 +42,10 @@ #include #include #include +#include +#include + +#include "eeprom.h" DECLARE_GLOBAL_DATA_PTR; @@ -71,7 +77,7 @@ static u32 gpmc_nand_config[GPMC_MAX_REG] = { /* * Routine: board_init - * Description: Early hardware init. + * Description: hardware init. */ int board_init(void) { @@ -96,12 +102,34 @@ int board_init(void) return 0; } +static u32 cm_t3x_rev; + +/* + * Routine: get_board_rev + * Description: read system revision + */ +u32 get_board_rev(void) +{ + if (!cm_t3x_rev) + cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); + + return cm_t3x_rev; +}; + /* * Routine: misc_init_r * Description: display die ID */ int misc_init_r(void) { + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); dieid_num_r(); return 0; @@ -235,9 +263,45 @@ static void cm_t3x_set_common_muxconf(void) MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ + /* USB EHCI */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ + + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + + /* SB_T35_USB_HUB_RESET_GPIO */ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ + /* I2C1 */ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ + /* I2C2 */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ + /* I2C3 */ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ /* control and debug */ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ @@ -315,7 +379,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif @@ -353,16 +417,17 @@ static void reset_net_chip(void) { /* Set GPIO1 of TPS65930 as output */ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO+0x03); + TWL4030_BASEADD_GPIO + 0x03); /* Send a pulse on the GPIO pin */ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO+0x0C); + TWL4030_BASEADD_GPIO + 0x0C); udelay(1); twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO+0x09); - udelay(1); + TWL4030_BASEADD_GPIO + 0x09); + mdelay(40); twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO+0x0C); + TWL4030_BASEADD_GPIO + 0x0C); + mdelay(1); } #else static inline void reset_net_chip(void) {} @@ -382,11 +447,9 @@ static int handle_mac_address(void) if (rc) return 0; -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - rc = i2c_read(0x50, 0, 1, enetaddr, 6); + rc = cm_t3x_eeprom_read_mac_addr(enetaddr); if (rc) return rc; -#endif if (!is_valid_ether_addr(enetaddr)) return -1; @@ -408,7 +471,7 @@ int board_eth_init(bd_t *bis) rc1 = handle_mac_address(); if (rc1) - printf("CM-T3x: No MAC address found\n"); + printf("No MAC address found! "); rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); if (rc1 > 0) @@ -421,3 +484,57 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +void __weak get_board_serial(struct tag_serialnr *serialnr) +{ + /* + * This corresponds to what happens when we can communicate with the + * eeprom but don't get a valid board serial value. + */ + serialnr->low = 0; + serialnr->high = 0; +}; + +#ifdef CONFIG_USB_EHCI_OMAP +struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +#define SB_T35_USB_HUB_RESET_GPIO 167 +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + u8 val; + int offset; + + if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { + printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", + SB_T35_USB_HUB_RESET_GPIO); + return -1; + } + + gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); + udelay(10); + gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); + udelay(1000); + + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; + twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset); + /* Set GPIO6 and GPIO7 of TPS65930 as output */ + val |= 0xC0; + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset); + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; + /* Take both PHYs out of reset */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset); + udelay(1); + + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + return omap_ehci_hcd_stop(); +} + +#endif /* CONFIG_USB_EHCI_OMAP */