X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcogent%2Fmb.h;h=b3aba48f7f29a30ee12b31e1839f347547fc1f95;hb=4a207e8b9a1ecc3e87d5a63bb5442dbcd50bd4b6;hp=f6eaf0ac5ee8839b360c21aa175fec90088b908e;hpb=da93ed8147a000505ac7b7ed4e2fb50532596a3c;p=u-boot

diff --git a/board/cogent/mb.h b/board/cogent/mb.h
index f6eaf0ac5e..b3aba48f7f 100644
--- a/board/cogent/mb.h
+++ b/board/cogent/mb.h
@@ -69,51 +69,51 @@
  * 0xA000000-0xDFFFFFF.
  */
 
-#define CMA_MB_RAM_BASE		(CFG_CMA_MB_BASE+0x0000000)
+#define CMA_MB_RAM_BASE		(CONFIG_SYS_CMA_MB_BASE+0x0000000)
 #define CMA_MB_RAM_SIZE		0x2000000	/* dip sws set actual size */
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
-#define CMA_MB_SLOT1_BASE	(CFG_CMA_MB_BASE+0x2000000)
+#define CMA_MB_SLOT1_BASE	(CONFIG_SYS_CMA_MB_BASE+0x2000000)
 #define CMA_MB_SLOT1_SIZE	0x2000000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2_BASE	(CFG_CMA_MB_BASE+0x4000000)
+#define CMA_MB_SLOT2_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
 #define CMA_MB_SLOT2_SIZE	0x2000000
 #endif
 #if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_STDPCI_BASE	(CFG_CMA_MB_BASE+0x4000000)
+#define CMA_MB_STDPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
 #define CMA_MB_STDPCI_SIZE	0x1ff0000
-#define CMA_MB_V360EPC_BASE	(CFG_CMA_MB_BASE+0x5ff0000)
+#define CMA_MB_V360EPC_BASE	(CONFIG_SYS_CMA_MB_BASE+0x5ff0000)
 #define CMA_MB_V360EPC_SIZE	0x10000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3_BASE	(CFG_CMA_MB_BASE+0x6000000)
+#define CMA_MB_SLOT3_BASE	(CONFIG_SYS_CMA_MB_BASE+0x6000000)
 #define CMA_MB_SLOT3_SIZE	0x2000000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
-#define CMA_MB_EXTPCI_BASE	(CFG_CMA_MB_BASE+0xa000000)
+#define CMA_MB_EXTPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0xa000000)
 #define CMA_MB_EXTPCI_SIZE	0x4000000
 #endif
 
-#define CMA_MB_ROMLOW_BASE	(CFG_CMA_MB_BASE+0xe000000)
+#define CMA_MB_ROMLOW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
 #define CMA_MB_ROMLOW_SIZE	0x800000
 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLLOW_EXEC_BASE	(CFG_CMA_MB_BASE+0xe000000)
+#define CMA_MB_FLLOW_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
 #define CMA_MB_FLLOW_EXEC_SIZE	0x100000
-#define CMA_MB_FLLOW_RDWR_BASE	(CFG_CMA_MB_BASE+0xe400000)
+#define CMA_MB_FLLOW_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe400000)
 #define CMA_MB_FLLOW_RDWR_SIZE	0x400000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
-#define CMA_MB_RTC_BASE		(CFG_CMA_MB_BASE+0xe800000)
+#define CMA_MB_RTC_BASE		(CONFIG_SYS_CMA_MB_BASE+0xe800000)
 #define CMA_MB_RTC_SIZE		0x4000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-#define CMA_MB_SERPAR_BASE	(CFG_CMA_MB_BASE+0xe900000)
+#define CMA_MB_SERPAR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900000)
 #define   CMA_MB_SERIALB_BASE	  (CMA_MB_SERPAR_BASE+0x00)
 #define   CMA_MB_SERIALA_BASE	  (CMA_MB_SERPAR_BASE+0x40)
 #define   CMA_MB_PARALLEL_BASE	  (CMA_MB_SERPAR_BASE+0x80)
@@ -121,20 +121,20 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
-#define CMA_MB_PKBM_BASE	(CFG_CMA_MB_BASE+0xe900100)
+#define CMA_MB_PKBM_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900100)
 #define CMA_MB_PKBM_SIZE	0x10
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
-#define CMA_MB_LCD_BASE		(CFG_CMA_MB_BASE+0xeb00000)
+#define CMA_MB_LCD_BASE		(CONFIG_SYS_CMA_MB_BASE+0xeb00000)
 #define CMA_MB_LCD_SIZE		0x10
 #endif
 
-#define CMA_MB_DIPSW_BASE	(CFG_CMA_MB_BASE+0xec00000)
+#define CMA_MB_DIPSW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xec00000)
 #define CMA_MB_DIPSW_SIZE	0x10
 
 #if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
-#define CMA_MB_SLOT1CFG_BASE	(CFG_CMA_MB_BASE+0xf100000)
+#define CMA_MB_SLOT1CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf100000)
 #if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
 #define   CMA_MB_SER2_BASE	  (CMA_MB_SLOT1CFG_BASE+0x80)
 #define     CMA_MB_SER2B_BASE	    (CMA_MB_SER2_BASE+0x00)
@@ -152,7 +152,7 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2CFG_BASE	(CFG_CMA_MB_BASE+0xf200000)
+#define CMA_MB_SLOT2CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
 #if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
 #define   CMA_MB_S2KBM_BASE	  (CMA_MB_SLOT2CFG_BASE+0x200)
 #endif
@@ -160,7 +160,7 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_PCICTL_BASE	(CFG_CMA_MB_BASE+0xf200000)
+#define CMA_MB_PCICTL_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
 #define   CMA_MB_PCI_V3CTL_BASE	  (CMA_MB_PCICTL_BASE+0x100)
 #define   CMA_MB_PCI_IDSEL_BASE	  (CMA_MB_PCICTL_BASE+0x200)
 #define   CMA_MB_PCI_IMASK_BASE	  (CMA_MB_PCICTL_BASE+0x300)
@@ -171,19 +171,19 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3CFG_BASE	(CFG_CMA_MB_BASE+0xf300000)
+#define CMA_MB_SLOT3CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf300000)
 #if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
 #define   CMA_MB_S3KBM_BASE	  (CMA_MB_SLOT3CFG_BASE+0x200)
 #endif
 #define CMA_MB_SLOT3CFG_SIZE	0x400
 #endif
 
-#define CMA_MB_ROMHIGH_BASE	(CFG_CMA_MB_BASE+0xf800000)
+#define CMA_MB_ROMHIGH_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
 #define CMA_MB_ROMHIGH_SIZE	0x800000
 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLHIGH_EXEC_BASE	(CFG_CMA_MB_BASE+0xf800000)
+#define CMA_MB_FLHIGH_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
 #define CMA_MB_FLHIGH_EXEC_SIZE	0x100000
-#define CMA_MB_FLHIGH_RDWR_BASE	(CFG_CMA_MB_BASE+0xfc00000)
+#define CMA_MB_FLHIGH_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xfc00000)
 #define CMA_MB_FLHIGH_RDWR_SIZE	0x400000
 #endif