X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcpc45%2Fplx9030.c;h=3711ccbd3c0b00377942ee932145fcb3db5640c4;hb=c3e17d5c9e73ca20d309277897f7ddfabf3dd3d0;hp=e337bd200b432123b7c14f1c4e19418ed12b8ab6;hpb=3bac351370ef7cbf9d2af27ba52bee1703ad677e;p=u-boot

diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c
index e337bd200b..3711ccbd3c 100644
--- a/board/cpc45/plx9030.c
+++ b/board/cpc45/plx9030.c
@@ -54,7 +54,7 @@ registers (CS3) on CPC45.
 
 /* PLX9030 register offsets  */
 #define	P9030_LAS0RR	0x00
-#define	P9030_LAS1RR 	0x04
+#define	P9030_LAS1RR	0x04
 #define	P9030_LAS2RR	0x08
 #define	P9030_LAS3RR	0x0c
 #define	P9030_EROMRR	0x10
@@ -72,8 +72,8 @@ registers (CS3) on CPC45.
 #define	P9030_CS1BASE	0x40
 #define	P9030_CS2BASE	0x44
 #define	P9030_CS3BASE	0x48
-#define	P9030_INTCSR 	0x4c
-#define	P9030_CNTRL  	0x50
+#define	P9030_INTCSR	0x4c
+#define	P9030_CNTRL	0x50
 #define	P9030_GPIOC	0x54
 
 /* typedefs */
@@ -137,7 +137,7 @@ void Plx9030Init (void)
 	sysOutLong((membaseCsr + P9030_LAS0BA),  0x00000001);		/* enable space base */
 	sysOutLong((membaseCsr + P9030_LAS0RR),  0x0FE00000);		/* 2 MByte */
 	sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900);		/* 4 wait states */
-	sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);		/* enable 2 MByte */	
+	sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);		/* enable 2 MByte */
 	/* remap CS0 (SRAM) */
 	pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
 
@@ -145,7 +145,7 @@ void Plx9030Init (void)
 	sysOutLong((membaseCsr + P9030_LAS1BA),  0x00400001);		/* enable space base */
 	sysOutLong((membaseCsr + P9030_LAS1RR),  0x0FFFFF00);		/* 256 byte */
 	sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900);		/* 4 wait states */
-	sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);		/* enable 256 Byte */	
+	sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);		/* enable 256 Byte */
 	/* remap CS1 (ST16552 / CHAN A) */
 	/* remap CS1 (ST16552 / CHAN A) */
 	pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
@@ -154,7 +154,7 @@ void Plx9030Init (void)
 	sysOutLong((membaseCsr + P9030_LAS2BA),  0x00800001);		/* enable space base */
 	sysOutLong((membaseCsr + P9030_LAS2RR),  0x0FFFFF00);		/* 256 byte */
 	sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900);		/* 4 wait states */
-	sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);		/* enable 256 Byte */	
+	sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);		/* enable 256 Byte */
 	/* remap CS2 (ST16552 / CHAN B) */
 	pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
 
@@ -162,7 +162,7 @@ void Plx9030Init (void)
 	sysOutLong((membaseCsr + P9030_LAS3BA),  0x00C00001);		/* enable space base */
 	sysOutLong((membaseCsr + P9030_LAS3RR),  0x0FFFFF00);		/* 256 byte */
 	sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80);		/* 9 wait states */
-	sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);		/* enable 256 Byte */	
+	sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);		/* enable 256 Byte */
 	/* remap CS3 (DISPLAY and BCSR) */
 	pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
 }
@@ -171,4 +171,3 @@ void sysOutLong(ulong address, ulong value)
 {
 	*(ulong*)address = cpu_to_le32(value);
 }
-