X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcray%2FL1%2FL1.c;h=8a06ecc66504e91f4aa4b8b3577c826e62a9b3b2;hb=0d8cb9c04facc029baf4beee5a7e389be343a915;hp=2babd2d358ac37dd3534be8d48d4ccb548c900ea;hpb=f61f1e150c84f5b9347fca79a4bc5f2286c545d2;p=u-boot

diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 2babd2d358..8a06ecc665 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -164,7 +164,7 @@ int misc_init_r (void)
 			setenv ("ethaddr", e);
 		}
 	}
-	sprintf (bootcmd,"autoscript %X",(unsigned)bootscript);
+	sprintf (bootcmd,"source %X",(unsigned)bootscript);
 	setenv ("bootcmd", bootcmd);
 	return (0);
 }
@@ -205,13 +205,13 @@ static void init_sdram (void)
 /* To set the appropriate timings, we need to know the SDRAM speed.	*/
 /* We can use the PLB speed since the SDRAM speed is the same as	*/
 /* the PLB speed. The PLB speed is the FBK divider times the		*/
-/* 405GP reference clock, which on the L1 is 25Mhz.			*/
-/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is	*/
-/* 150Mhz; if FBK is 3, SDRAM is 150Mhz.				*/
+/* 405GP reference clock, which on the L1 is 25MHz.			*/
+/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is	*/
+/* 150MHz; if FBK is 3, SDRAM is 150MHz.				*/
 
 	/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
 
-/* write SDRAM timing for 100Mhz. */
+/* write SDRAM timing for 100MHz. */
 	mtdcr (memcfga, mem_sdtr1);
 	mtdcr (memcfgd, 0x0086400D);