X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcsb272%2Fcsb272.c;h=24c6f0d9869f6940f563398f361ab1aae9a85c0e;hb=83a49c8dd7998be2d1f0d420597a36bbf0bf4164;hp=fecd7e8ef387620dd09db9c5b570d44e74bf11a4;hpb=42dfe7a1844cbad7114038aaf03828acb7a84414;p=u-boot diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index fecd7e8ef3..24c6f0d986 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -25,7 +25,7 @@ #include #include #include -#include <405gp_enet.h> +#include /* * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator @@ -164,10 +164,15 @@ long initdram (int board_type) int last_stage_init(void) { /* initialize the PHY */ - miiphy_reset(CONFIG_PHY_ADDR); - miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */ - miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */ + miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); + + /* AUTO neg */ + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + + /* LEDs */ + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); + return 0; /* success */ }