X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fcsb472%2Fcsb472.c;h=b1de18ce51ed193dd7d51f8dce9e787d440dd4ec;hb=ecfc19f31f1fa25f739d11c81d4810f9b35b29aa;hp=996a67b4edc4ba559eb6fb48d73cb15cabfcbe01;hpb=83653121d7382fccfe329cb732f77f116341ef1d;p=u-boot

diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index 996a67b4ed..b1de18ce51 100644
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -2,30 +2,14 @@
  * (C) Copyright 2004
  * Tolunay Orkun, Nextio Inc., torkun@nextio.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/processor.h>
 #include <i2c.h>
 #include <miiphy.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
 
 void sdram_init(void);
 
@@ -97,7 +81,7 @@ phys_size_t initdram (int board_type)
 	/*
 	 * ToDo: Move the asm init routine sdram_init() to this C file,
 	 * or even better use some common ppc4xx code available
-	 * in arch/ppc/cpu/ppc4xx
+	 * in arch/powerpc/cpu/ppc4xx
 	 */
 	sdram_init();
 
@@ -144,11 +128,11 @@ int last_stage_init(void)
 	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 
 	/* AUTO neg */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
-			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
 
 	/* LEDs     */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
 
 	return 0; /* success */
 }